STT MRAM Highlights from IEDM 2019

STT MRAM Highlights from IEDM 2019
by Don Draper on 01-02-2020 at 6:00 am

IEDM 2019 Logo

IEDM 2019 had the theme: “Innovative Devices for an Era of Connected Intelligence” of which MRAM is a leading contributor.  Following a very informative Plenary Session, Monday afternoon led off with Session 2: Memory Technology – STT-MRAM.  This session has seven important STT-MRAM papers describing the progress of this … Read More


A VIP to Accelerate Verification for Hyperscalar Caching

A VIP to Accelerate Verification for Hyperscalar Caching
by Bernard Murphy on 12-18-2019 at 6:00 am

NVMe

Non-volatile memory (NVM) is finding new roles in datacenters, not currently so much in “cold storage” as a replacement for hard disk drives, but definitely in “warm storage”. Warm storage applications target an increasing number of functions requiring access to databases with much lower latency than is possible through paths… Read More


KLAC- Very Strong Sept & Guide-Foundry up 50%- 5NM & EUV drivers- Outperforming

KLAC- Very Strong Sept & Guide-Foundry up 50%- 5NM & EUV drivers- Outperforming
by Robert Maire on 11-05-2019 at 6:00 am

  • KLAC Strong Beat on Both Sept Q & Dec Guide
  • Foundry/logic (TSMC) up 50% H2 vs H1
  • Gen 5 acceptance and 5NM rollout drive future

Strong beat in Sept results and Dec Guide
KLAC reported revenue of $1.41B and EPS of $2.48 handily beating street estimates of $1.5B and $2.20 in EPS. More importantly the company guided December to be revenues… Read More


WEBINAR: Generating and Measuring IP Security Threat Levels For Your SoCs

WEBINAR: Generating and Measuring IP Security Threat Levels For Your SoCs
by Daniel Nenni on 10-09-2019 at 6:00 am

IPs have an attack surface that indicates how they can be compromised in real world scenarios. Some portions of the attack surfaces are well known, others are discovered during analysis, testing or out in the field. SoCs that use large collections of IPs need a systematic and reliable way to determine the various security vulnerabilities… Read More


WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!

WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!
by Daniel Nenni on 09-02-2019 at 10:00 am

With every process node and every SOC design, engineering and IT teams are experiencing an unprecedented data explosion. User workspaces routinely exceed 10’s of GB and sometimes even 100’s of GB. Regression runs, characterization runs, design and debug of workspaces, building verification environments – all of these… Read More


China Winning the Future of the semiconductor industry?

China Winning the Future of the semiconductor industry?
by Bart van Hezewijk on 09-01-2019 at 11:00 am

In this second article about China’s role in the global semiconductor industry I analyse the impact of the Chinese government’s Big Fund and compare Chinese investments in semiconductor R&D with those in other countries. In my previous article, I looked at the possible effects of a US-China decoupling in theRead More


A Brief History of Methodics

A Brief History of Methodics
by Daniel Nenni on 04-29-2019 at 12:00 pm

Methodics has been a key player in IP management for over 10 years. In this section, Methodics shares their history, technology, and their role in developing IP Lifecycle Management (IPLM) solutions for the electronics industry.

Methodics is recognized as a premier provider of IP Lifecycle Management (IPLM) and traceability… Read More


A Brief History of IP Management

A Brief History of IP Management
by Daniel Nenni on 04-24-2019 at 12:00 pm

As RTL design started to increase in the late 1980’s and early 1990’s, it was becoming apparent that some amount of management was needed to keep track of all the design files and their associated versions. Because of the parallels to software development, design teams looked to the tools and methodologies that were in use by software… Read More


Traceability and Design Verification Synergy

Traceability and Design Verification Synergy
by Daniel Payne on 03-14-2019 at 12:00 pm

The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability… Read More


How Well Did Methodics do in 2018?

How Well Did Methodics do in 2018?
by Daniel Payne on 02-27-2019 at 12:00 pm

In January I read from the ESDA Allianceabout EDA and Semiconductor IP revenues increasing 6.7% for Q3 2018, reaching $2,435.6 million, which is decent growth for our maturing industry. In stark contrast there’s a company called Methodicsthat specializes in Intellectual Property Lifecycle Management (IPLM) and traceability… Read More