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2024 Outlook with John Lee, VP and GM Electronics, Semiconductor and Optics Business Unit at Ansys

2024 Outlook with John Lee, VP and GM Electronics, Semiconductor and Optics Business Unit at Ansys
by Daniel Nenni on 03-21-2024 at 10:00 am

John Lee Headshot

We have been working with Ansys since SemiWiki was founded in 2011. It has been a richly rewarding relationship in all regards. I always say the semiconductor industry is filled with the most intelligent people in the world and Ansys is an excellent proof point. I have known John Lee for 30+ years and he is one of my trusted few, absolutely.… Read More


Simulating the Whole Car with Multi-Domain Simulation

Simulating the Whole Car with Multi-Domain Simulation
by Bernard Murphy on 03-21-2024 at 6:00 am

Simulating the Whole Car with Multi-Domain Simulation

Next significant automotive blog in a string I will be posting (see here for the previous blog).

In the semiconductor world, mixed simulation means mixing logic sim, circuit sim, virtual sim (for software running on the hardware we are designing) along with emulation and FPGA prototyping. While that span may seem all-encompassing,… Read More


QuantumPro unifies superconducting qubit design workflow

QuantumPro unifies superconducting qubit design workflow
by Don Dingee on 03-20-2024 at 10:00 am

Superconducting qubit design workflow in QuantumPro

To create quantum computing chips today, a typical designer must cobble various tools together, switching back and forth between them for different tasks. By contrast, EDA solutions such as Keysight Advanced Design System (ADS) unify a design workflow in a single interface with automated data exchange between features. In … Read More


sureCore Enables AI with Ultra-Low Power Memory IP

sureCore Enables AI with Ultra-Low Power Memory IP
by Mike Gianfagna on 03-20-2024 at 8:00 am

sureCore Enables AI with Ultra Low Power Memory IP

We all know that AI is becoming pervasive in a wide array of products to make them smarter, safer and feature rich. Just look at the announcements from the recent CES show in Las Vegas to see some examples. These AI workloads demand a lot of compute power. Fueling this trend is the need for significant arrays of embedded memory on chip,… Read More


Challenge and Response Automotive Keynote at DVCon

Challenge and Response Automotive Keynote at DVCon
by Bernard Murphy on 03-20-2024 at 6:00 am

dvcon 2024 keynote min

Keynotes commonly provide a one-sided perspective of a domain, either customer-centric or supplier-centric. Kudos therefore to Cadence’s Paul Cunningham for breaking the mold in offering the first half of his keynote to Anthony Hill, a TI fellow, to talk about outstanding challenges he sees in verification for automotive … Read More


Unleash the Power: NVIDIA GPUs, Ansys Simulation

Unleash the Power: NVIDIA GPUs, Ansys Simulation
by Daniel Nenni on 03-19-2024 at 10:00 am

Electromagnatic PerceiveEM

In the realm of engineering simulations, the demand for faster, more accurate solutions to complex multiphysics challenges is ever-growing.

Simulation is a vital tool for engineers to design, test, and optimize complex systems and products. It helps engineers reduce costs, improve quality, and accelerate innovation. However,… Read More


Synopsys Enhances PPA with Backside Routing

Synopsys Enhances PPA with Backside Routing
by Mike Gianfagna on 03-19-2024 at 6:00 am

Comparison of frontside and backside PDNs (Source IMEC)

Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side… Read More


Afraid of mesh-based clock topologies? You should be

Afraid of mesh-based clock topologies? You should be
by Daniel Payne on 03-18-2024 at 10:00 am

mesh-based clock topology

Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More


Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?

Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?
by Mike Gianfagna on 03-18-2024 at 6:00 am

Can Correlation Between Simulation and Measurement be Achieved for Advanced Designs?

“What you simulate is what you get.” This is the holy grail of many forms of system design. Achieving a high level of accuracy between predicted and actual performance can cut design time way down, resulting in better cost margins, time to market and overall success rates. Achieving a high degree of confidence in predicted performance… Read More


Measuring Local EUV Resist Blur with Machine Learning

Measuring Local EUV Resist Blur with Machine Learning
by Fred Chen on 03-17-2024 at 10:00 am

Measuring Local EUV Resist Blur with Machine Learning

Resist blur remains a topic that is relatively unexplored in lithography. Blur has the effect of reducing the difference between the maximum and minimum doses in the local region containing the feature. Blur is particularly important for EUV lithography since EUV lithography is prone to stochastic fluctuations and also driven… Read More