AI Models on Edge GPUs
Semiconductor Expert Forum

Podcast EP377: Aion Silicon’s Growth and Impact Across Multiple Markets with Oliver Jones

Podcast EP377: Aion Silicon’s Growth and Impact Across Multiple Markets with Oliver Jones
by Daniel Nenni on 11-06-2026 at 12:00 pm
Categories: Aion Silicon, Semiconductor Services

Daniel is joined by Oliver Jones, CEO of Aion Silicon, a global semiconductor design and engineering company delivering custom silicon solutions for the AI age. He leads the company’s strategy and growth as it continuously helps technology companies bring advanced SoC designs to market from architecture through production,… Read More

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ChipNexus Brings Agentic AI into Established Analog Design Flows

ChipNexus Brings Agentic AI into Established Analog Design Flows
by Daniel Nenni on 11-06-2026 at 10:00 am
Categories: ChipNexus, EDA

Agentic AI for Analog Chip Design

ChipNexus has introduced its NEX Analog Agent, bringing conversational automation to analog engineering workflows built around Cadence Virtuoso, Spectre simulation and Siemens Calibre physical verification. Available now, the software operates with customers’ installed tools, licenses and process design kits, giving… Read More

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Delivering Silicon Systems Through AI Disruption, Part 2: The Conductor

Delivering Silicon Systems Through AI Disruption, Part 2: The Conductor
by Joel Jorgensen on 11-06-2026 at 8:00 am
Categories: Flow Accel, Semiconductor Services

The Conductor SemiWiki 3360x1888

Conductor: the person who keeps every section of the orchestra in time without playing an instrument. In this article, it’s your operating model.

In Part 1, I wrote about the score, your designed workflows across the three layers Gene Kim and Steven Spear describe in Wiring the Winning Organization: the technical work, … Read More

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WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs

WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs
by Daniel Nenni on 11-06-2026 at 6:00 am
Categories: Events, Imagination Technologies, IP

Edge GPU AI webinar banner

Modern AI models are opening up new possibilities at the edge. Turning those possibilities into responsive, efficient applications, however, requires more than choosing hardware with an impressive TOPS figure. Developers need to understand how models behave on their target devices, where performance is lost, and which optimisations… Read More

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Interview with David Tester VP of Engineering Mach42

Interview with David Tester VP of Engineering Mach42
by Daniel Nenni on 11-05-2026 at 12:00 pm
Categories: CEO Interviews, EDA, Mach42

Pre Silicon Problems David Tester Interview

David Tester is the VP of Engineering at Mach42, with 30 years of experience in semiconductor development, engineering leadership, and business growth. As Chief Engineer at EnSilica, he helped transform the company from a design consultancy into a publicly listed fabless semiconductor business, scaling the organisation … Read More

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Glass Is Becoming an AI Infrastructure Platform

Glass Is Becoming an AI Infrastructure Platform
by Moh Kolb on 11-05-2026 at 10:00 am
Categories: 3D IC, Chiplet

Glass substrate as arch SemiWiki oct5 (1) (1)

The value of glass will be determined not by its material properties alone, but by whether it can expand the package architecture window and be realized repeatedly at manufacturing scale.

AI infrastructure is pushing advanced packaging into a regime where the substrate itself increasingly determines what can be built.

As packages… Read More

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Ceva and Mobilint Bring Physical AI Closer to Everyday Devices

Ceva and Mobilint Bring Physical AI Closer to Everyday Devices
by Daniel Nenni on 11-05-2026 at 8:00 am
Categories: Ceva, IP

REGULUS Powers the Intelligent Factory

Physical AI is moving closer to everyday reality, and a new collaboration between Ceva and Mobilint offers an encouraging example of how that progress can reach commercial devices. Mobilint’s REGULUS edge AI System-on-Chip brings together Ceva’s SensPro AI DSP and NeuPro-Nano NPU, marking the first production deployment … Read More

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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival

The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
by Kalar Rajendiran on 11-05-2026 at 6:00 am
Categories: 3D IC, AI, Chiplet, EDA, IP, Synopsys
1 Comment

The Real Value of Predictable Execution

The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More

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CTO Interview with Taylor Barton of Certus Semiconductor

CTO Interview with Taylor Barton of Certus Semiconductor
by Daniel Nenni on 11-04-2026 at 12:00 pm
Categories: AI, Automotive, CEO Interviews, Certus Semiconductor, IP

Smaller footprint, greater possibility

Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering… Read More

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Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity  

Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity  
by Admin on 11-04-2026 at 10:00 am
Categories: Defacto Technologies, EDA

By Defacto Staff

Today’s chips are no longer just processors, they are entire systems. A System-on-Chip (SoC) brings together CPU clusters, accelerators, memories, interconnects and dozens of peripherals, often coming from many different teams and vendors. With AI, high-performance computing and IoT driving demand for … Read More