UWB Without the Integration Headache: Ceva and LG Bring Precision to More ChipsCeva and LG Electronics have joined forces to…Read More
PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI ConnectivityBy Tim Messegee, Senior Director of Solutions Marketing…Read More
Semiconductor Engineering Has a State-Continuity ProblemProduct realization depends not only on reaching the…Read More
Samtec Puts AI’s Interconnect Bottleneck on Display at ECOC and AI Infra SummitSamtec is using two major 2026 industry events…Read More
Nvidia Sees AGI While OpenAI Sees DangerJensen Huang’s declaration that “AGI has arrived” is…Read More
Weebit Nano’s FY26 ESG Report shows how sustainability, governance and operational resilience are becoming integrated into the company’s commercialisation of resistive random-access memory (ReRAM). This integration matters because Weebit’s value is not derived from manufacturing and selling finished chips directly.… Read More
Chip-on-Wafer-on-Substrate, commonly called CoWoS, is an advanced packaging platform developed by TSMC. It allows processors, chiplets, and high-bandwidth memory stacks to be integrated within a single package. CoWoS has become especially important for artificial-intelligence accelerators and high-performance computing… Read More
Artificial intelligence is moving rapidly from an experimental aid to a foundational part of semiconductor engineering. In a recent industry talk, leaders from ChipAgents and Analog Devices described how agentic AI could help chipmakers manage soaring design complexity, accelerate product development, and improve the … Read More
Co-packaged optics is usually described as a proximity problem.
Move the optical engine closer to the switch ASIC or XPU. Shorten the electrical path. Reduce SerDes power. Increase bandwidth density.
That direction is real.
Optical functionality is moving progressively closer to compute.
But proximity does not eliminate … Read More
Analog Bits is expanding its role in advanced semiconductor design with new intellectual property aimed at one of the industry’s most difficult problems: delivering, monitoring, and managing power inside increasingly complex chips.
The company announced that its IP will be included in an upcoming customer test-chip tapeout… Read More
By Prof. Dr. S. Filo Ambrosini
On a semiconductor line, a rising defect rate can trigger a familiar debate. Do we need a new inspection system? More sensors? An additional engineer?
Those may all be valid responses. But before making the decision, someone needs to establish when the change began, where it first appears, and whether… Read More
Broadcom’s fiscal third-quarter 2026 results show how artificial-intelligence infrastructure is shifting from general-purpose acceleration toward customized compute and large-scale networking. The company reported AI semiconductor revenue of $16.7 billion, up 221% year over year and 54% sequentially. That expansion… Read More
Raghu co-founded Enphase Energy with Martin Fornage in 2006. He has more than 25 years of experience in the clean energy and high‑technology industries, and has been at the forefront of developing Enphase’s leading integrated energy system—with solar generation, storage, monitoring, and control. Prior to Enphase, Raghu developed
Daniel is joined by Matthew Ozalas from Keysight. With an experience of more than 20 years, Matthew brings a plethora of knowledge in complex RF designs using CAD tools. Matthew has also authored several application notes on RF and Microwave design and development using Keysight ADS with his recent ones based on “Artificial … Read More
TSMC reportedly plans to double its Chip-on-Wafer-on-Substrate capacity from approximately 130,000 300mm-equivalent wafers per month at the end of 2026 to 260,000 by 2028. The estimate is not formal company guidance and should be treated as a supply-chain projection. Nevertheless, the direction is consistent with TSMC’s… Read More
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ASML Has High-NA and Chipmakers Can’t Say No