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Automating and Optimizing an ADC with Layout Generators

Automating and Optimizing an ADC with Layout Generators
by Daniel Payne on 08-24-2022 at 10:00 am

Layout Geneator tool flow min

I first got involved with layout generators back in 1982 while at Intel, and about 10% of a GPU was automatically generated using some code that I wrote. It was an easy task for one engineer to complete, because the circuits were digital, and no optimization was required. In an IEEE paper from the 2022 18th International ConferenceRead More


Hazard Detection Using Petri Nets. Innovation in Verification

Hazard Detection Using Petri Nets. Innovation in Verification
by Bernard Murphy on 08-24-2022 at 6:00 am

Innovation New

Modeling and verifying asynchronous systems is a constant challenge. Petri net models may provide an answer. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The

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EDA Product Mix Changes as Hardware-Assisted Verification Gains Momentum

EDA Product Mix Changes as Hardware-Assisted Verification Gains Momentum
by Lauro Rizzatti on 08-23-2022 at 10:00 am

Semiwiki Hero Image Lauro Rizzatti

The Design Automation Conference, as always, is a good barometer on the state of EDA and my area of interest, verification. The recent DAC offered plenty of opportunities to check on trends and the status quo.

Remarkably, exhibitors and attendees were upbeat about the chip design landscape despite concerns about supply chain … Read More


WEBINAR: A Revolution in Prototyping and Emulation

WEBINAR: A Revolution in Prototyping and Emulation
by Daniel Nenni on 08-23-2022 at 6:00 am

MimicPro Picture

This webinar will introduce to you a revolutionary new way to do prototyping and emulation at best-in-class performance, productivity, and pricing by unifying the hardware and a new software stack so one system is capable of prototyping and delivering essential emulation functionality.

Register Here

The speed of Moore’s law… Read More


A clear VectorPath when AI inference models are uncertain

A clear VectorPath when AI inference models are uncertain
by Don Dingee on 08-22-2022 at 10:00 am

Achronix VectorPath Accelerator Card with Speedster 7t1500 FPGA for running AI inference models and more

The chase to add artificial intelligence (AI) into many complex applications is surfacing a new trend. There’s a sense these applications need a lot of AI inference operations, but very few architects can say precisely what those operations will do. Self-driving may be the best example, where improved AI model research and discovery… Read More


Protecting Critical IP With Next-Generation Zero Trust Security

Protecting Critical IP With Next-Generation Zero Trust Security
by Kalar Rajendiran on 08-22-2022 at 6:00 am

Securing Access Controls

While semiconductors are the enablers for high-tech solutions, the semiconductor industry was not at the forefront of Cloud adoption. There were many valid concerns behind the slow adoption, a primary reason being the threat to intellectual property (IP) security. IP in this context refers to not just chip building blocks but… Read More


Podcast EP102: A Brief History of eFPGA with Geoff Tate of Flex Logic

Podcast EP102: A Brief History of eFPGA with Geoff Tate of Flex Logic
by Daniel Nenni on 08-19-2022 at 10:00 am

Dan is joined by Geoff Tate, CEO and Co-founder of Flex Logix. Geoff explains the embedded FPGA market, including some history, applications and challenges to deliver a product that customers really want. He provides some very relevant background on why Flex Logix has been so successful in this market, and what lies ahead.

GEOFF… Read More


An EDA AI Master Class by Synopsys CEO Aart de Geus

An EDA AI Master Class by Synopsys CEO Aart de Geus
by Daniel Nenni on 08-19-2022 at 8:00 am

Aart de Geus White House

I consider Dr. Aart de Geus one of the founding fathers of EDA and one of the most interesting people in the semiconductor industry. So it is not a surprise that Aart was chosen to attend the CHIPs Act signing at the White House.

Here is his current corporate bio:

Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys… Read More


CEO Interview: Jay Dawani of Lemurian Labs

CEO Interview: Jay Dawani of Lemurian Labs
by Daniel Nenni on 08-19-2022 at 6:00 am

JayDawani

Jay Dawani is the co-founder & CEO at Lemurian Labs, a startup developing a novel processor to enable autonomous robots to fully leverage the capabilities of modern day AI within their current energy, space, and latency constraints.

Prior to founding Lemurian, Jay had founded two other companies in the AI space. He is also … Read More