From Faster Proofs to Trusted Silicon with LUBIS EDALUBIS EDA is introducing FormalOS, a platform designed…Read More
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This year’s Future of Memory and Storage Conference (formerly the Flash Memory Summit) was again very well attended. The Santa Clara Convention Center is definitely the place to be for a Silicon Valley Conference.
This post is about the Emerging Memories session organized by Dave Eggleston. We will be covering other sessions… Read More
The semiconductor industry is experiencing a significant transformation with the advent of chiplet design, a modular approach that breaks down complex chips into smaller, functional blocks called chiplets. A chiplet-based design approach offers numerous advantages, such as improved performance, reduced development … Read More
Zeev Collin is a seasoned technology executive and serial entrepreneur with over 25 years of experience in executive management across international semiconductor companies and startups. Prior to co-founding Semitech, Zeev co-founded and successfully exited two ventures focused on vehicle and trailer tracking devices.… Read More
When designing IP for system-on-chip (SoC) and application-specific integrated circuit (ASIC) implementations, IP designers strive for perfection. Optimal engineering often yields the smallest die area, thereby reducing both cost and power consumption while maximizing performance.
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A familiar face in EDA, Greg Lebsack met with me in the Empyrean booth at DAC this year on opening day to provide an update on what’s new. I first met Greg when he was at Tanner EDA, then Mentor and Siemens EDA, so he really knows our industry quite well. The company was a Silver level sponsor of DAC this year, and Empyrean offers tools for… Read More
The demand for high-performance and sustainable computing and networking silicon for AI has undoubtedly increased R&D dollars and the pace of innovation in semiconductor technology. With Moore’s Law slowing down at the chip level, there is a desire to pack as many chiplets as possible inside ASIC packages and get … Read More
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With all the Q2-24 results delivered, it is time to remove the clouds of euphoria and panic, ignore the performance claims and the bugs, and analyse the Data Center business, including examining the supply chain up and downstream. It is time to find out if the AI boom in semiconductors is still alive.
We begin the analysis with the … Read More
Dan is joined by Dr. Mark Han, Vice President of R&D Engineering for Circuit Simulation at Synopsys. Mark leads a team of over 300 engineers in developing cutting-edge advanced circuit simulation and transistor-level sign-off products, including characterization and static timing analysis. With 27 years of industry … Read More
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