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Formal For All!
“Do I need a PhD to use formal verification?”
“Can formal methods really scale?”
“Is it too difficult to write formal properties that actually prove something?”
“If I can’t get a proof, should I just hope for the best?”
“Do formal methods even offer useful coverage metrics?”
Discouraging words to say the least, but… Read More
The annual ITC event is happening this week in San Diego as semiconductor test professionals gather from around the world to discuss their emerging challenges and new approaches, so last week I had the opportunity to get an advance look at something new from Siemens named Tessent In-System Test software. Jeff Mayer, Product Manager,… Read More
I just read an interesting white paper on functional verification of analog blocks using SV-RNM (SystemVerilog real number modeling). The content is worth the effort to read closely as it elaborates a functional verification flow for RNM matching expectations for digital logic verification, from randomization to functional… Read More
Flexible LCD technology has spurred a wave of creativity in device design, including a new class of foldable phones and an update to the venerable flip phone. Besides the primary display inside the fold – sometimes taking the entire inside area – a smaller secondary display is often found outside the fold. Introducing the secondary… Read More
The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.
KLA reported… Read More
Dan is joined by Dr. Emre Ozer, Senior Director of Processor Development at Pragmatic Semiconductor. With 67 worldwide patents, and over 60 peer-reviewed publications to his name, he has extensive experience in CPU microarchitecture with particular expertise in performance modelling, fault tolerant CPUs, embedded machine… Read More
Dan is joined by Ciaran Whyte, one of the founding members of IC Mask Design. As Chief Technical Officer he is responsible for all technical activity and the development and administration of all training courses. Cíaran has been training layout engineers for over 25 years and has completed layout training with over 600 engineers… Read More
Previously, Dr. Carter served as Chief Commercial Officer at Foxconn Interconnect and Oclaro. At Oclaro, he served as a member of the senior executive team from July 2014 to December 2018, when it was acquired by Lumentum Holdings for $1.85B. Prior to that, he served as the Senior Director and General Manager of the Transceiver… Read More
I’ve been working with AMIQ EDA for several years, and have frequently been impressed by new capabilities in their Design and Verification Tools Integrated Development Environment (DVT IDE) family. They just announced AI Assistant, which leverages large language model (LLM) technology. LLMs are much in the news these days,… Read More
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?