Zebu flow Engineer

The Role:

• The successful candidate will join SiFive’s System Validation team, which is responsible for the building flow for modelling SiFive’s RISC-V CPUs on Emulators like Synopsys Zebu. This role extends beyond Emulators and will work with other FPGA based platforms and flows. .
• This position offers significant exposure to RISC-V processors, the RISC-V software ecosystem, and various development boards, providing exceptional learning opportunities for engineers pursuing a career in the RISC-V domain.

Responsibilities

• Build and maintain a modular flow for building Synopsys ZeBu models using the SiFive internal build system. This includes transitioning compilation steps into the SiFive wake-based build environment to support seamless integration with other internal flows.
• Execute root cause and failure analysis across RISC-V CPU hardware and software components.
• Facilitate debug using ZeBu features like waveform dumping and utilize ILA and JTAG debuggers to troubleshoot and validate designs.
• Develop failure hypotheses through systematic, step-by-step elimination of potential causes.
• Create and support Python-based scripts to enhance and automate debug workflows, and support the integration of ZeBu runtime automation into the SiFive manager ecosystem.
• Work cross-functionally and maintain active partnership with both the software and validation engineering departments.

Requirements:

• 1+ years of experience with a Bachelor’s or Master’s degree in Computer Science or Electronics and Communication Engineering is required.
• A strong understanding of logic design is essential.
• Prior exposure to logic design using Verilog and the subsequent porting of designs onto FPGA platforms is necessary.
• Practical experience with Linux-based operating systems and scripting languages such as Python and BASH is mandatory.
• Candidates must possess a positive attitude, a proactive approach to continuous learning, and a commitment to achieving excellence in their work.