Webinar: The “bridge” to scale for AI and HPC applications

Designing high-performance multi-chiplet semiconductor packages for hyperscale, HPC and AI applications combines cutting-edge innovation with practical optimization. Embedded silicon bridge substrates enable cost-effective solutions by using base substrates such as organic laminates or redistribution-layer (RDL) buildup, helping overcome the reticle-size and cost limitations of monolithic silicon substrates.

Embedded silicon bridges provide power-efficient, high-speed connections between chiplets and memory, delivering the massive bandwidth required for AI parallelism and hyperscale/HPC energy-efficiency demands. Key challenges remain, including inter-chiplet connectivity, thermal dissipation and power integrity.

In this webinar, Siemens EDA and Intel Foundry will introduce embedded bridge technology and its market applications. Intel Foundry will present its EMIB and EMIB-T technology offerings, followed by a demonstration of the Siemens reference flow for Intel Foundry EMIB and EMIB-T technologies.

What you will learn:

• What is driving the demand for more than Moore in IC design
• How substrate-embedded silicon bridges enable efficient, cost-effective heterogeneous integration and silicon scaling
• An introduction to Intel Foundry’s proven Embedded Multi-die Interconnect Bridge (EMIB) technologies
• How a single-vendor, integrated and certified workflow supports Intel Foundry EMIB and EMIB-T technologies

Who should attend:

• IC and IC package verification managers and directors
• IC and IC package design managers and 3D IC program leads
• CAD and methodology managers
• IC, chiplet, semiconductor package and substrate designers
• System and micro architects
• Verification engineers working in physical verification, SI/PI, reliability, thermal and stress analysis

Products covered:

• Innovator3D IC Integrator
• Questa FormalPro
• Calibre 3DThermal
• Calibre 3DStack
• Innovator3D IC Layout
• HyperLynx SI/PI

REGISTER HERE