Staff Engineer – CPU Verification

Key Responsibilities

• Verification Strategy: Define and execute comprehensive verification plans for CPU sub-systems (e.g., Load/Store units, Memory Management Units, or Execution Pipelines).
• Testbench Development: Build and maintain advanced, scalable verification environments using UVM (Universal Verification Methodology) and SystemVerilog.
• Test Content Creation: Develop constrained-random stimulus, directed tests, and assembly-level tests to achieve rigorous coverage targets.
• Debug & Analysis: Lead complex debugging efforts at the unit and SOC levels, identifying architectural and RTL bugs.
• Mentorship: Provide technical leadership and guidance to junior verification engineers, ensuring best practices in coding and verification logic.

Required Skills & Qualifications:

• Experience: 7+ years of experience in ASIC/SOC verification, specifically focused on CPU or complex IP blocks.
• Technical Proficiency: knowledge of System Verilog and UVM.
• Architecture Knowledge: Strong understanding of Computer Architecture (pipelines, caches, out-of-order execution, and memory consistency models).
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

• Experience with the RISC-V or ARM/x86 ISA and CPU verification experience