Staff Design Verification Engineer – Cache Verification

The Role

SiFive is looking for a Staff Design Verification Engineer to drive verification of cache and memory-subsystem functionality, with an emphasis on cache coherency, ordering, correctness, and subsystem integration.

This is a Staff Engineer individual-contributor role within the horizontal cache verification area. We are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the team.

Responsibilities

• Own verification planning and execution for L2/L3 cache and related cache-subsystem features, from block-level verification through subsystem integration.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for cache coherency, ordering, flow control, and error scenarios.
• Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, backpressure, and integration behavior.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate closely with architecture, design, and verification teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.
• Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC, CPU, or SoC design verification, with strong hands-on ownership of complex verification problems at block or subsystem level.
• Strong expertise in SystemVerilog and UVM-based verification.
• Strong understanding of cache architecture, memory hierarchy, and cache coherency protocols/behavior.
• Experience building reusable testbenches, assertions, checkers, scoreboards, coverage models, and debug infrastructure.
• Strong debugging skills with the ability to root-cause issues across specification, RTL, and testbench layers.
• Experience with coverage analysis and closure, constrained-random verification, and metrics-driven signoff.
• Strong understanding of computer architecture and microarchitecture fundamentals.

Preferred Qualifications

• Direct experience verifying multiple levels of cache, including private and shared cache structures.
• Experience with cache coherency, memory consistency, weak ordering, and multicore verification challenges.
• Experience with performance-oriented verification, formal techniques, or emulation/FPGA-assisted debug.
• Familiarity with Python, C/C++, or scripting languages used for DV infrastructure and automation.
• Ability to influence technical direction across architecture, design, and verification teams.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to real architectural risk areas.
• Critical cache and coherency bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and verification quality improve meaningfully under your ownership.
• The cache verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Architecture and design teams rely on you as a strong technical partner for difficult verification and debug problems.