Senior Design Verification Engineer – Cache Verification

About the Role

SiFive is looking for a Senior Design Verification Engineer to drive verification of cache and memory-subsystem functionality, with an emphasis on cache coherency, ordering, correctness, and subsystem integration.

This is a Senior Engineer individual-contributor role within the horizontal cache verification area. We are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the team.

Responsibilities

• Understand the cache and memory-subsystem architecture and create effective verification strategies and test plans for the assigned area.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for cache coherency, ordering, flow control, and error scenarios.
• Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, backpressure, and integration behavior.
• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.
• Collaborate closely with architecture, design, and verification teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.
• Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 3+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in CPU, memory-system, or cache verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering concepts.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Strong problem-solving skills and the ability to work effectively across design and verification teams.

Preferred Qualifications

• Direct experience verifying cache or memory-subsystem functionality, including coherency behavior in multicore systems.
• Experience with subsystem integration and protocol interactions across multiple interfaces or bridge paths.
• Familiarity with scripting and automation using Python or similar languages.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug is a plus.

What Success Looks Like

• Verification plans are complete and aligned with the highest architectural risks.
• Critical bugs are found early, debugged efficiently, and closed with durable fixes.
• Coverage and verification quality improve meaningfully under your ownership.
• The cache verification effort becomes more scalable, reusable, and predictable because of your contributions.