Director Front End Engineering

Job Description:
Signoff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. Signoff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.
Signoff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada) and California (US) in order to serve its customer based on their asks & needs.

Front end Director

• Would be responsible for development and execution on Design, DFT, and Verification, FPGA based design and development.
• This role is primarily based in Bangalore with interaction and driving teams within India and globally.
• The role will involve delivery and execution.
• Driving the team and methodologies and requires hands on experience in all aspects and stages of Design, frontend/backend, DFT, and Verification.

Responsibilities:

• Fully own the Design, DFT, Verification for Subsystems/SOCs from Initial specification through TapeOut and beyond.
• Driving FPGA and ASIC RTL/DFT/Verification Sign off, timing constraints, CDC and work with different functions like verification, synthesis, etc. to get to a production quality Silicon.
• Leading various aspects of Test architecture including Scan & ATPG, Memory BIST, Logic BIST, Analog/PHY test and post-silicon support with test pattern generation.
• Manage, build, and develop teams of fresh and experienced engineers.
• Train and mentor fresh engineers for increased productivity.
• Build up strong collaboration with other R& D teams like Architecture, SOC.
• Responsible for people development, goal setting and team performance.
• Developing project plans including resource, schedules, progress reports, verification plans, signoff checklists and tracking milestones.
• Holding periodic internal and external reviews to ensure quality and meet delivery criteria.
• Working with various EDA vendors to deploy next gen Design technologies.
• Ensure quality adherence during all stages of the project life cycle.
• Ensure that correct metrics are established to measure the Design Verification processes and goals.
• Power Management Understanding

Requirements:

• BTech /MTech with 15+ years’ experience in Semiconductor industry.
• Candidate should be an experienced manager having experience of leading a team in SoC Design and Verification.
• Experience of SoCs based on ARM Core Architecture, RISC V,  etc.
• Experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
• Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, security and other architectures.
• Experience of working on Gate Level Sims with strong concepts of CDC, RDC, Power Aware GLS.
• Low Power intent verification using CPF, UPF.
• Power management understanding, including techniques for optimizing design for Ultra Low Power.
• FPGA/Emulation/Prototyping