Dolphin is addressing the ultra-low-power (ULP) needs for some applications, like for example Bluetooth low energy (BLE), machine-to-machine (M2M) or IoT edge devices in general. For these applications, defining active and sleep modes is imperative, but it may not be enough to guarantee that the battery-powered system will run for years, especially when the device integrates Always-On functions. In fact, a device in sleep mode is expected to support some mandatory functions, like Clock (RC or XTAL oscillator), retention SRAM (data and program memory), ACU/PMU logic (control), voice activity detection and so on. We will see in this webinar the different strategies to implement these Always-On functions, including the power network distribution within the chip.
It’s a very practical webinar, as Dolphin propose different architectures, all based on IP from Dolphin port-folio (in 180 nm, 55nm, 40nm and 22nm processes) dedicated to Always-On power domain, and discuss the impact on the chip power consumption by using measured (or simulated) power figures.
Dolphin proposes five synopses, each related to a specific action:
- –Using a supply multiplexer
- –Mutualizing a voltage regulator
- –Associating 2 voltage regulators
- –Using a near-threshold voltage library
- –Using a thick oxide library
The designer will go for the architecture optimized in respect with the application constraints, probably mixing several of the above listed recipes.
The emerging connected systems are most frequently battery-powered and the goal is to design a system able to survive with, for example, a coin cell battery, not for days or even months, but for years. If you dig, you realize that numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC. For such applications, the design of the “Always-On power domain” is pivotal. To meet customer expectations, ensuring a current consumption of the Always-On (AoN) power domain – incl. blocks in retention mode – not higher than 500 nA is pivotal. To reach this target, the power network architecture needs to be carefully considered, and the IP supporting this architecture available in the target technology node.
Dolphin has developed a methodology based on a figure of merit (FoM), expressed as follow:
Because we are dealing with devices supporting always-on capability in the context of connected, battery powered system, the weight value is the highest for power consumption with 60%, decrease to 25% for area and 15% for bill-of-material (BoM). Looking at the five power architectures to implement the AoN power domain, a comparative analysis will enable to identify the characteristics of silicon IPs required to reach the targeted performance optimization, identified by the best (lower is better) FoM.
We can see a real example, with 3 cases of Bluetooth LE chips (BLE1, BLE2, BLE3), on the above picture. In the three cases, the active current is the same (the same BLE function is integrated), and only the sleep current value is different with resp. 10, 1 and 0.2 uA. If you consider a system active only 1% of the time (or 15 min per day), the battery autonomy varies from 208 days (10 uA sleep) to 260 days (0.2 uA sleep). The difference is much more impressive with a system active only 1 minute per day: in this case, the battery autonomy can reach up to 5 years for the lowest sleep current (0.2 uA) case, or 3 times more than for the highest sleep current (10 uA) case with a battery autonomy of 1.7 years.
Dolphin will hold a live webinar “Recipe to consume less than 0.5 µA in sleep mode” on May 23 for Americas, at 9:00 AM PDT or June 1[SUP]st[/SUP] (for Europe or Asia), at 11:00 AM CEST. This webinar targets the SoC designers wanting to learn how to quickly implement ultra-low power (uLP) techniques, using proven recipes.
You can access to the record of this webinar by registering to MyDolphin, the private space of Dolphin Integration’s website:
By Eric Esteve from IPNEST
More about the various architecture allowing to implement ultra-low-power solutions: