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CEVA Fortrix™ SecureD2D IP: Securing Communications between Heterogeneous Chiplets

CEVA Fortrix™ SecureD2D IP: Securing Communications between Heterogeneous Chiplets
by Kalar Rajendiran on 02-17-2022 at 10:00 am

Discussions of chiplets has been on the rise, ever since the slowdown of Moore’s law benefits. Gartner Research projects semiconductor revenue from systems using chiplets to grow from $3.3 billion in 2020, to $50.5 billion in 2024. With any market opportunity, there are always challenges to overcome in order to realize the full potential. The chiplets market opportunity is no exception. Consequentially, a lot of development is happening to successfully support chiplets based design, methodology and integration.

First things first. What are chiplets? Chiplets are the multiple smaller dies we end up with after architecturally disintegrating a large integrated circuit or a SoC. Conceptually a chiplets-based design resembles a Silicon-In-Package (SiP) based design. SiP-based approach was historically adopted primarily for faster time to market by mixing and matching dies of pre-existing chips. And, typically the pre-existing chips are from the same vendor. While the mixing and matching part is true with chiplets too, the full market opportunity lies with heterogenous chiplets integration. Heterogeneous in this context means chiplets from different vendors. This aspect in itself raises lots of concerns with adoption, system security being one of them.

CEVA’s recently announced Fortrix SecureD2D IP addresses the above concern by securing die-to-die communications between chiplets in a heterogeneous SoC (HSoC). CEVA is well known for its technologies in wireless connectivity, smart sensing and sensor fusion, AI & Deep Learning, computer vision and audio processing. The Fortrix IP expands CEVA’s offerings into the system and IP platform space.

Before we diving into the details of the Fortrix IP, there is an interesting story to share about the early origins of this IP.

Over the recent past, the slowdown of Moore’s law benefits has been limiting the adoption of SoCs by the defense sector too. Realizing this, the Department of Defense (DoD) had launched the CHIPS program a few years ago. CHIPS stands for Common Heterogeneous Integration and Intellectual Property Reuse Strategies. The vision for this program was to conceive an ecosystem of discrete, modular, reusable IP which can be assembled into a secure system. For example, with a chiplets implementation, how to ensure die-to-die communications are safe and secure? How to guarantee a secure boot and protect against counterfeit chiplets? How to protect against firmware tampering? With the semiconductor supply chain distributed across the globe, possible breach of security and trust is a real concern. On the successful completion of the CHIPS program, DoD launched the SHIP program. SHIP stands for State-of-the-art Heterogeneous Integration Prototype.

Intrinsix (now a wholly-owned subsidiary of CEVA) customized the Fortrix SecureD2D IP for the SHIP program. If there is one industry that literally lives and breathes security and trust, that would be the defense industry. The Fortrix IP is now available for both commercial and defense oriented applications.  

CEVA Fortrix SecureD2D IP Solution

The CEVA FortrixTM is a hardware/software platform for developing secure chiplet based systems. The Fortrix SecureD2D IP offers secure authentication and firmware boot/code load between chiplets, and ensures system level security in a HSoC. The solution consists of a controller communicating over a secure fabric to hardware-based crypto accelerators. The accelerators support rapid encryption and decryption of functions including ECDSA, SHA2, and AES. The controller is embedded in all the chiplets within the HSoC.

Fortrix Controller Block Diagram

Fortrix Controller Block Diagram CEVA Chiplet

The chiplet containing the system host can be either an ASIC or an FPGA. The firmware for the companion chiplets is stored in a protected area of the host chiplet. A dedicated SPI bus connects the chiplets for establishing a crypto-secure channel. After authentication of the companion chiplet, the encrypted firmware is sent from the host to the companion chiplet. The Fortrix IP platform comes with a low-level API and a sample application for quick and easy customization of the IP.

Refer to the following block diagram to see how the chiplets are integrated within a HSoC.

HSoC Architecture Block Diagram

Foxtrix Architecture Block Diagram

Benefits of Fortrix IP Platform

  • Protects against various security threats
  • Allows for threat protection expansion as threats evolve
  • Ease of incorporation into a HSoC
  • Efficient Crypto engines are very efficient in terms of compute cycles and power consumption

IP Availability

Fortrix SecureD2D IP is available for licensing today. Deliverables include RTL, SDC constraints, firmware and documentation. Customers desiring integration services can tap into CEVA’s design services offering for a full HSoC design and delivery.

You can read the full press release about the Fortrix IP here. You can learn more about it at the product page.

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