Webinar: Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis

Webinar: Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
by Admin on 12-26-2023 at 8:13 pm

The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones.

One way to improve efficiency is to… Read More


Webinar: Leveraging the CHIPS Act in the Silicon Heartland: Ohio Semiconductor Industry Initiatives

Webinar: Leveraging the CHIPS Act in the Silicon Heartland: Ohio Semiconductor Industry Initiatives
by Admin on 12-06-2023 at 4:55 pm

Leveraging the CHIPS Act in the Silicon Heartland: Ohio Semiconductor Industry Initiatives

SEMI has invited key stakeholders from Ohio to discuss state initiatives that can be leveraged in alignment with current and upcoming CHIPS Funding opportunities. Webinar participants will learn why Ohio is a premier location for semiconductor… Read More


CHIPS R&D Digital Twin Technical Standards Workshop

CHIPS R&D Digital Twin Technical Standards Workshop
by Admin on 11-28-2023 at 5:05 pm

Technical standards for digital twin capabilities in the semiconductor and microelectronics industry will be the subject of a December workshop sponsored by the CHIPS Research and Development Office. The workshop will be a hybrid in-person and virtual event from 8:30 a.m. to 5:30 p.m. Eastern Time December 14, 2023, and 8:30… Read More


CHIPS R&D Chiplets Interfaces Technical Standards Workshop

CHIPS R&D Chiplets Interfaces Technical Standards Workshop
by Admin on 11-28-2023 at 5:03 pm

The CHIPS Research and Development Office’s Chiplets Interfaces Technical Standards Workshop will be held as a hybrid in-person and virtual event from 8:30 a.m. to 5:30 p.m. Eastern Time December 12, 2023, and 8:30 am to 12:30 pm December 13, 2023.  This event will bring together technical experts from industry, academia, standards… Read More


Designing Chips with CHIPS: West Coast Pre-Silicon Summit

Designing Chips with CHIPS: West Coast Pre-Silicon Summit
by Admin on 10-25-2023 at 2:34 pm

3 November 2023 | San Diego, California

We all know the CHIPS Act will have a profound impact on manufacturing in the U.S., but what about Chip Design & Packaging?

The Designing Chips with CHIPS: West Coast Pre-Silicon Summit is a one-day semi summit that will bring together leading thinkers from chip design and packaging companies,

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Webinar: System-Level Thermal Signoff from Chips Through to Racks

Webinar: System-Level Thermal Signoff from Chips Through to Racks
by Admin on 09-25-2023 at 3:26 pm

Title: WEBINAR l System-Level Thermal Signoff from Chips Through to Racks

Date: Wednesday, October 18, 2023

Time: 10:00 AM Eastern Daylight Time

Duration: 45 minutes

Summary

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and

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Webinar: IP Lifecycle Management for Chiplet-Based SoCs

Webinar: IP Lifecycle Management for Chiplet-Based SoCs
by Admin on 08-02-2023 at 2:56 pm

Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges… Read More


Webinar: System-Level Thermal Signoff from Chips Through to Racks

Webinar: System-Level Thermal Signoff from Chips Through to Racks
by Admin on 03-16-2023 at 2:34 pm

Date: Thursday, April 27, 2023

Time: 10:00am PT/1:00pm ET

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature

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