PCIe Gen 6 Verification IP Speeds Up Chip Development

PCIe is a prevalent and popular interface standard that is used in just about every digital electronic system. It is used widely in SOCs and in devices that connect to them. Since it was first released in 2003, it has evolved to keep up with rapidly accelerating needs for high speed data transfers. Each version has doubled in throughput, with updates coming every few years – except for the notable gap between version 3.0 and 4.0. PCIe Gen 6 is expected to be have its final release in 2021.

PCIe Gen 6 supports 126 GB/s in each direction when using 16 lanes. The individual lane speed will be 7.87 GB/s. Many changes were made in the specification to achieve these data rates. Most significant of these is the change to PAM-4 (pulse amplitude modulation with four levels) and the addition of ECC. Numerous other changes were made to the protocol as well. As is always the case, PCIe Gen 6 interfaces will be backward compatible with earlier versions to ensure interoperability. All of this is good news to system designers in need of higher bandwidth and flexibility.

However, these changes mean that designing and verifying complete and correct functionality has become even more difficult. Lots of system designers will choose to use IP blocks to help implement PCIe Gen 6 in their designs. Whether or not the interface controller and PHY are developed in house or outsourced, complete verification is a necessity.

Developing a test suite takes a level of effort on par with or greater than developing the PCIe IP itself. Fortunately, Truechip, a developer of verification IP(VIP), offers a complete test suite and verification environment for PCIe Gen 6. Their VIP is fully compliant with the latest PCIe Gen 6 specifications. It is built, using years of experience, to be lightweight, with an easy plug-and-play interface to ensure rapid deployment.

Their PCIe test bench includes agents for the Root Complex and the Device Endpoint. They each come with bus functional models for the TL, DL and PHY layers. In addition, there is a PCIe Bus Monitor which performs many useful operations. It supports assertions, coverage, as well as checkers for the TL, DL and PHY. All of this is connected to a scoreboard to help monitor test results.

The test bench is backward compatible with all of the relevant earlier specifications. It supports precoding for 32GT/s and 64GT/s, PAM-4 signaling, FLIT and non-FLIT mode and the new PIPE 6.0 specification. It can be configured to support from x1 to x32 link widths. All low power management states, including the new L0p state are available. The list of features in the documentation and data sheet is comprehensive and supports every feature in the specification.

To ensure comprehensive validation the test environment and test suite provide a wide range of tests. Users can run basic and directed protocols tests. There are also random tests and error scenario tests. Truechip includes assertions and cover point tests. Lastly there are compliance tests, to ensure the finish product will work smoothly with other PCIe devices. There is a full set of documentation that goes through the integration process and can be used as a reference guide during use.

The time frame for bringing PCIe Gen 6 devices to market is fast approaching. Truechip has already had customer deliveries for this VIP product. Having ready to go VIP can make a big positive impact on the development and testing schedules for products that rely on PCIe Gen6. With PCIe playing such a large role in SOCs and device operation, it is crucial to support the latest standard and be able to offer the highest interoperability, quality and reliability. Truechip offers much more information about their PCIe Gen 6 VIP on their website. If you are developing products that rely on PCIe Gen 6, it might be worth a look.

Also read:

Bringing PCIe Gen 6 Devices to Market

USB4 Makes Interfacing Easy, But is Hard to Implement

TrueChip CXL Verification IP

Webinar Replay on TileLink from Truechip