You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Common channel structure, around which drains gates and sources are built up. The channel itself is either structured first, or deep RIE cut through multiple drain/gate/source layers, and filled in.
First functioning demonstrators of stacked VTFETs were made in research labs decades ago.
Do you have a reference for that demonstrator, I have never heard of that and never heard/seen anyone talk about it and I am very plugged in to that community.
Do you have a reference for that demonstrator, I have never heard of that and never heard/seen anyone talk about it and I am very plugged in to that community.
They aren’t explicitly called out as VTFETs. The papers he is referring to all came from universities and are titled something to the tune of monolithic 3D cmos, cmos 2.0, and the most well developed concept paper was called skybridge. I am pretty sure all of the work has been very basic proof of concept silicon or coventor sims. Among other issues, I don’t really know how anyone is supposed to make random structures of logic with that design. But if nothing else it is a cool intellectual curiosity.
My own, I have been analyzing this path for many years, I have a presentation of over 60 slides that walks through the whole path and has been shared with/reviewed by a select group of experts.
since CFET is 2 trannies in same space, that calculation implies 1300 sq nm per unit cell or something like 30 x 45nm, credible given > 5 years from now.
since CFET is 2 trannies in same space, that calculation implies 1300 sq nm per unit cell or something like 30 x 45nm, credible given > 5 years from now.
It not quite 2x density due to interconnect requirements but it is a big jump. 2D gives a big jump in CPP and therefore cell width, and CFET gives a big jump in cell height by doubling up the transistors and eliminating the horizontal n-p spacing.
It not quite 2x density due to interconnect requirements but it is a big jump. 2D gives a big jump in CPP and therefore cell width, and CFET gives a big jump in cell height by doubling up the transistors and eliminating the horizontal n-p spacing.
We’ve had this very discussion before. Every single BSP paper out there uses tungsten not copper. Scotten has talked about resistance from chipmakers on BPR due to the fact that the tungsten gets laid out first. But you must keep in mind if it was copper then this technology would go from challenging to flat out impossible. As far as I remember intel has not talked about when in the flow powervias are made and TSMC has not publicly stated what BSPD scheme they are using.
They aren’t explicitly called out as VTFETs. The papers he is referring to all came from universities and are titled something to the tune of monolithic 3D cmos, cmos 2.0, and the most well developed concept paper was called skybridge. I am pretty sure all of the work has been very basic proof of concept silicon or coventor sims. Among other issues, I don’t really know how anyone is supposed to make random structures of logic with that design. But if nothing else it is a cool intellectual curiosity.
Aluminum for what, are you talking Buried Power Rail (BPR) because Al won't survive the temperatures or meet the electromigration requirements. If you are talking Backside Power Delivery that is copper and it is done at the end of the process flow.
We are running 3nm now with 2nm (20A) due 2024 to 2026 depending on version and company. Samsung has talked about 1.4nm in 2027 based on a Horizontal Nanosheet with more sheets. My projections are 10A around 2029 based on a CFET, with 7A, 5A, and 3A CFETs to follow. Finally around 2037 we get CFETs with 2D and that is the 1,500MTx/mm2. All the pitches are achievable with High NA EUV.
Aluminum for what, are you talking Buried Power Rail (BPR) because Al won't survive the temperatures or meet the electromigration requirements. If you are talking Backside Power Delivery that is copper and it is done at the end of the process flow.
