Why FDSOI?

[cliff]

I get some customer calls about supporting GF22 fdsoi. They say it's rad-hard. Good for satellites. Then they want redundancy. Best 2 out of 3 voting, etc. Why bother? Why not just go with a better valued process and package the SIP in lead?

France/EU is putting $6B or so into 22/18 fdsoi. Why?

 

[IanD]

I get some customer calls about supporting GF22 fdsoi. They say it's rad-hard. Good for satellites. Then they want redundancy. Best 2 out of 3 voting, etc. Why bother? Why not just go with a better valued process and package the SIP in lead?

France/EU is putting $6B or so into 22/18 fdsoi. Why?

Because for some applications it's a very good process...

 

[Nish]

The soi wafer guys, soitec, is French. Also, EU fabs like ST and GF(Dresden) gave up on leading edge development and instead rather focus on specialty tech like soi. So yeah there is a lot of soi marketing/lobbying going around in EU.

 

[IanD]

The soi wafer guys, soitec, is French. Also, EU fabs like ST and GF(Dresden) gave up on leading edge development and instead rather focus on specialty tech like soi. So yeah there is a lot of soi marketing/lobbying going around in EU.

Indeed there is -- but customers won't use it because of marketing, they'll use it because it's the best choice for what they want to do.

SOI has significant advantages over bulk silicon in some application areas including RF and rad-hard/high-temperature. If it didn't, nobody would use it.

And yes these applications are smaller volume than the mass-market ones like mobile AP and CPUs and HPC/networking and many others, which is why SOI is only a small part of the CMOS market.

 

[Nish]

Indeed there is -- but customers won't use it because of marketing, they'll use it because it's the best choice for what they want to do.

SOI has significant advantages over bulk silicon in some application areas including RF and rad-hard/high-temperature. If it didn't, nobody would use it.

And yes these applications are smaller volume than the mass-market ones like mobile AP and CPUs and HPC/networking and many others, which is why SOI is only a small part of the CMOS market.

Definitely, I wasn't refuting your point, I was just adding to it. Soi (not just fdsoi) has many niche uses including RF and optical; and with Europe hosting most of the supply chain, they have decided to market, lobby, focus and develop on this.

 

[cliff]

I am comparing FDSOI to the 16-12nm processes, not bulk silicon. With a probable glut in 16-12nm, why make a new 22fdsoi fab to be ready in 2026?

When you are saying RF, you are specifically talking about a heterodyne receiver (mixing down to baseband), correct? You believe you cannot capture the signal with interleaving ADCs in 16nm?

 

[IanD]

I am comparing FDSOI to the 16-12nm processes, not bulk silicon. With a probable glut in 16-12nm, why make a new 22fdsoi fab to be ready in 2026?

When you are saying RF, you are specifically talking about a heterodyne receiver (mixing down to baseband), correct? You believe you cannot capture the signal with interleaving ADCs in 16nm?

I'm not talking about any specific RF circuit. We're using 22FDX for wideband analogue circuits (which we refer to as "RF", for want of a better term) covering from DC to >70GHz...

(and yes these talk to ADCs/DACs running at >150Gsps, but these aren't on the 22FDX chip, they're on a 5nm FinFET DSP chip)

Horses for courses... ;-)

 

[cliff]

I am asking for specifics. Suppose you can pick between 16-12nm finfet (pick TSMC, GF, Intel) and gf22fdsoi for the same price. Let's suppose the layout time was identical and the EDA tool price and the mask cost is the same, you can put the package in lead, and exotic RAM was available on all processes, why would you pick 22fdsoi? What capability do you have in 22fdsoi that would make you pick that process. Please be specific. No hand waving

 

[IanD]

FDSOI has higher Ft for both NMOS and *especially* PMOS (for high-speed push-pull circuits) than FinFET, the BOX isolation reduces crosstalk and makes it easier to do device stacking for higher voltages, and the back gate can be used for Vth/offset voltage trimming.

For circuits where these are significant advantages, FDSOI is better -- sometimes considerably better -- than FinFET (all the way down to 5nm). The fact that the wafer cost may be a bit higher -- if it is -- is usually not an issue.

But this is all circuit-dependent, you need to do the comparison for your particular case -- it's no use asking for specific answers for a different case... ;-)

 

[nghanayem]

In theory 22FDSOI should be easier to layout and have a cheaper process flow (cost probably still slightly cheaper than N16 even though SOI wafers are more expensive) given it is planar. Leakage and clock speed won't be as good though as N16/i16 though. If the costs were literally equal I would go with N16 over all others unless GF or intel were giving me a specialized tech/qualification/memory tech that I needed that N16 doesn't have, or I really wanted the i16 clockspeeds.

 

[IanD]

In theory 22FDSOI should be easier to layout and have a cheaper process flow (cost probably still slightly cheaper than N16 even though SOI wafers are more expensive) given it is planar. Leakage and clock speed won't be as good though as N16/i16 though. If the costs were literally equal I would go with N16 over all others unless GF or intel were giving me a specialized tech/qualification/memory tech that I needed that N16 doesn't have, or I really wanted the i16 clockspeeds.

If all you care about is digital clock speed and cost, go with FinFET -- not because it's inherently cheaper (fewer masks vs. SOI cost) but because it's made in massive volume by TSMC not smaller volume by ST. There's also much more IP available from a lot more suppliers.

 

[Paul2]

Leakage figures of much smaller nodes while costing much cheaper

LP, and ULP MCUs are on FDSOI 40nm-55nm

 

[IanD]

Leakage figures of much smaller nodes while costing much cheaper

LP, and ULP MCUs are on FDSOI 40nm-55nm

You can use the back-gate to shift Vth between operating mode (faster, more leakage) and standby mode (slower, maybe 100x less leakage) -- this doesn't work in bulk (especially not FinFET). Since this can be done on a block-by-block basis it's very useful for things like ULP MCUs.

22FDX has some double-patterning (still a lot fewer masks than FinFET), 40nm and up is all single-patterned so cheaper (but lower performance for RF). Both are good for specific (but different) applications.

 

[cliff]

Thank you Ian, Paul, and Mr Ng. I also care about power, memory, tunability, calibration, eFPGAs, etc. Our engineering labor (design and layout) of 16/14, 22, 28, 40, and 65 are identical. I understand that you can tune the capacitance and Vt, but there are ways of tuning with finfets as well, or switching to a different block. We support 22fdsoi, but I am questioning it. The way I see it, finfet, HBM, 130/90nm (sige?), perhaps as interposer. Lead package for raditation. I am going out on a limb and speculating that 90-22 will be obsolete by the time Crolles is ready, unless the EU is planning on making a trade barrier. What say you?

Paul, please reword. I know finfets have the lowest leakage. Bulk went higher in leakage as the feature size went lower. Is that what you are saying? As far as price... ?

 

[IanD]

Thank you Ian, Paul, and Mr Ng. I also care about power, memory, tunability, calibration, eFPGAs, etc. Our engineering labor (design and layout) of 16/14, 22, 28, 40, and 65 are identical. I understand that you can tune the capacitance and Vt, but there are ways of tuning with finfets as well, or switching to a different block. We support 22fdsoi, but I am questioning it. The way I see it, finfet, HBM, 130/90nm (sige?), perhaps as interposer. Lead package for raditation. I am going out on a limb and speculating that 90-22 will be obsolete by the time Crolles is ready, unless the EU is planning on making a trade barrier. What say you?

Paul, please reword. I know finfets have the lowest leakage. Bulk went higher in leakage as the feature size went lower. Is that what you are saying? As far as price... ?

Why would 22FDX (or whatever) become "obsolete"?

Advanced FinFET processes have much higher digital density and speed *if this is what matters to your application*, which is why Apple and Qualcomm and AMD and Intel and Marvell use them. They also are very expensive to design in (including tools) and the NRE costs are enormous, so your business for a chip has to be big enough (>$100M?) to justify this and make the smaller chip size/higher density worth it.

None of this is going to take away the advantages of FDSOI now or in the future, either for lower volume/cost applications or where FDSOI gives a real advantage. It's like saying that as EVs get better they'll take the place of bicycles -- they won't, because the markets are completely different. We're using 22FDX and TSMC N5 for different purposes, neither can do the job of the other as well.

If 22FDX doesn't have such advantages for you, don't use it... ;-)

 

[jms_embedded]

We're using 22FDX and TSMC N5 for different purposes, neither can do the job of the other as well.

just curious, what order of magnitude volume + which market? (if you can say anything about either)

 

[IanD]

just curious, what order of magnitude volume + which market? (if you can say anything about either)

Can't... ;-)

 

[cliff]

Can you explain the NRE cost of $100M on a GF 14/12 vs GF22 for example.

Can we assume the the circuit designer costs are the same.
The layouts take 3x longer in finfet, is that correct?
The masks cost about, say 1.5x more in GF22 vs GF14?
EDA tools?

Use 16-12. Not (currently) insane processes

 

[IanD]

Can you explain the NRE cost of $100M on a GF 14/12 vs GF22 for example.

Can we assume the the circuit designer costs are the same.
The layouts take 3x longer in finfet, is that correct?
The masks cost about, say 1.5x more in GF22 vs GF14?
EDA tools?

I was talking about advanced FinFET processes (for example 5nm) not 12/14nm, because the question was about 22FDX becoming "obsoleted" by newer processes.

If you want to compare GF 12nm/14nm FinFET with 22FDX the FinFET mask costs are higher, there are more of them and more are double-patterned -- I don't have exact figures because we don't use GF FinFET, you need to ask GF.

As I keep saying, for "plain vanilla" digital 22FDX is probably not the right process -- but if you need the advantages it offers (e.g. for ULP or RF), it can be...

 

[Paul2]

Bulk went higher in leakage as the feature size went lower. Is that what you are saying?

It's relative, for the performance ranges, and frequencies of something like an MCU, or, say, display driver ASIC, you should get more leakage reduction per buck with SOI.