Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/why-fdsoi.17180/page-2
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Why FDSOI?

I get some customer calls about supporting GF22 fdsoi. They say it's rad-hard. Good for satellites. Then they want redundancy. Best 2 out of 3 voting, etc. Why bother? Why not just go with a better valued process and package the SIP in lead?
Lead is not magic. Arguably the best protection against radiation in space would be borated concrete, or borated water. Light nucleii give you more cross section per kg and nucleii such as boron and zirconium have anomalously high appetites for particular kinds of radiation. Lead is good for gamma rays, IIRC, not for cosmic rays or solar wind.

But you need a lot of shielding. The atmosphere at sea level is equivalent to 10m of water above us, and yet we still have significant radiation. Boron is much more effective, but you still need a lot of it and it does not stop all kinds of radiation.

So, if you want to go into space you need chips which are inherently resistant to radiation, which is not as difficult as you might think. Most radiation events are transient ionization with no structural damage, so what you want is a device which is not perturbed by radiation. This is why DRAM (with thousands of electrons per cell) is much less bothered by radiation than SRAM (where you can flip a junction with a much smaller electron cascade). So long as your device will not lock up or fuse on such electron bursts your chip will do pretty well. As for redundancy, in many cases what you need is just error detection and retry of transactional functionality. This can be as simple as the ECC in an SRAM or as complex as the retry mechanism in a database. The hard part is finding a general solution to detecting the error. Memory errors are easy - but how do you know if your multiplier just glitched? In practice the solution may be a combination of a tough process along with the usual case that logic gates are less susceptible to radiation than SRAM and spend most of their time in idle states which do not contribute to results, so the error rate will be very low.

In cases where it really, really matters and where there are real-time constraints on delivering safe results, that is where schemes like triplicated voting are essential.
 
22FDX has some double-patterning (still a lot fewer masks than FinFET), 40nm and up is all single-patterned so cheaper (but lower performance for RF). Both are good for specific (but different) applications.
Was the scaling of FDSOI below 22 stopped by physics, or would the architecture and advantages scale to smaller devices if the lithography were cheap enough to make sense?

I vaguely recall seeing some exploration of building fins on insulator to give a 3-sided channel control variant, but that was probably only in a lab?
 
In cases where it really, really matters and where there are real-time constraints on delivering safe results, that is where schemes like triplicated voting are essential.
So best 2 out of the 3 on unleaded 16nm?
 
Was the scaling of FDSOI below 22 stopped by physics, or would the architecture and advantages scale to smaller devices if the lithography were cheap enough to make sense?

I vaguely recall seeing some exploration of building fins on insulator to give a 3-sided channel control variant, but that was probably only in a lab?
Planar SOI can't go any further. Because while leakage is better than bulk planar, it is still far worse than finFETs. As for why besides GF and IBM nobody seems to care about finFET SOI that I don't really know. I know foundries and intel were originally going to, but they figured out how to do it without SOI and save a bunch of money. If memory serves like 15 or 20% on wafer costs at the time. My guess is that these days it is a smaller uptick due to SOI being more common than it used to be and the costs of nodes in the finFET era having gotten more expensive relative to their realizable density improvements.
 
costs of nodes in the finFET era having gotten more expensive relative to their realizable density improvements.
16-12nm is fairly priced. That is why I am asking the question. I don't understand the appeal of 22fdsoi. I haven't heard anything convincing yet, except a few people mentioned about special RAM, but I believe that will be available soon (perhaps now) on finfet technologies. My company put priority on automating finfet processes. I am questioning why I should take a step backwards and improve gf22, and why France committed $6B to developing this questionable technology. I am "asking the experts".
 
16-12nm is fairly priced. That is why I am asking the question. I don't understand the appeal of 22fdsoi. I haven't heard anything convincing yet, except a few people mentioned about special RAM, but I believe that will be available soon (perhaps now) on finfet technologies. My company put priority on automating finfet processes. I am questioning why I should take a step backwards and improve gf22, and why France committed $6B to developing this questionable technology. I am "asking the experts".
16-12nm are fair yes. But your price per yielded die area after factoring in design costs (especially early in the finFET era) wasn't quite as good as 28nm. My statement on cost was mostly talking about 10nm and above where the cost scaling is even worse. Of course don't misinterpret this cost per transistor is going up (it isn't). But we are a long way from the era of linear scaling, performance increases, and die shrinks justifying their cost.
 
I have seen a TSMC linear cost curve for yielded die from older technologies through 16nm. When you say "design costs", is the difference the EDA tool and layout time cost?
 
When you say "design costs", is the difference the EDA tool and layout time cost?
This is my understanding. But admittedly this is off of things I’ve seen people say on this very site. As I stated I would assume “design costs” today aren’t nearly as bad as they were now that people are used to finFETs and double patterning.
 
16-12nm is fairly priced. That is why I am asking the question. I don't understand the appeal of 22fdsoi. I haven't heard anything convincing yet, except a few people mentioned about special RAM, but I believe that will be available soon (perhaps now) on finfet technologies. My company put priority on automating finfet processes. I am questioning why I should take a step backwards and improve gf22, and why France committed $6B to developing this questionable technology. I am "asking the experts".
I'm not directly and technically addressing GF22FDX but general soi instead, also commenting more on the political side. Mainly about the question why France is putting lots of euros in soi. This wont answer why you must go back to support your 22FDX customers.

Soi is used a lot for photonic chips and there are trends for full optical-electrical integration that involve soi. eg. GFUS took their 45 RFSOI process and added photonics to it (45CLO) (after Ayar Labs already used it as zero-change). They also are working on 45 soi SiGe in a Darpa funded project(T-Music). Looks like we may see a GF 45 soi PIC+SiGe platform. ST has also published 28nm soi SiGe early work. IHP makes a 250nm soi PIC+SiGe platform too.

On the politics side, the large funding def smells of French nationalism. I am not sure if this article was discussed on this forum before:
 
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I'm not talking about any specific RF circuit. We're using 22FDX for wideband analogue circuits (which we refer to as "RF", for want of a better term) covering from DC to >70GHz...

(and yes these talk to ADCs/DACs running at >150Gsps, but these aren't on the 22FDX chip, they're on a 5nm FinFET DSP chip)

Horses for courses... ;-)
On a tangential note, i'm interested in high speed data converters - do you perhaps have any publicly available information on those >150Gsps 5nm converters?
 
On a tangential note, i'm interested in high speed data converters - do you perhaps have any publicly available information on those >150Gsps 5nm converters?
Nope, they're integrated into a DSP for coherent optics.
 
16-12nm is fairly priced. That is why I am asking the question. I don't understand the appeal of 22fdsoi. I haven't heard anything convincing yet, except a few people mentioned about special RAM, but I believe that will be available soon (perhaps now) on finfet technologies. My company put priority on automating finfet processes. I am questioning why I should take a step backwards and improve gf22, and why France committed $6B to developing this questionable technology. I am "asking the experts".
I already answered but you don't seem to have read what I wrote.

If all you want is standard digital, use TSMC FinFET.

If some of the particular 22FDX FDSOI features which FinFET can't offer (RF Ft, back-gate Vth tuning, ULP) have significant advantages for your customers (which outweigh any disadvantages), then you might want to support it.
 
Ian, I read what you wrote. We automated the GF22 process (analog, digital P&R, stdcells) and constructed SerDes, PLLs, ADCs, bandgaps, Pclamps, etc semi-automatically. We understand how to crudely tune VCOs through switches to caps and fine tuning them by changing the depletion region. We understand how to change the threshold by controlling the back gate. We also have S parameters, etc in our environment and we have analog in our name.

My intent is to gather as many reasons why circuit designers see the NEED of using the European process (Nish, I agree with you) and ensure that we can make a functionally equivalent version on the US based processes (FinFETs). I like putting as many circuit functions onto 1 chip, and I believe the speeds of 16-12nm processes can fetch (through interleaving) and process the incoming signals such that mixers, etc are a thing of the past. There are amazing things you can put onto one chip. Digital calibration makes analog more accurate. eFPGAs, CPUs with embedded SRAM are other features that are jammed into the same chip.

We have automated finFETs, so we have solved the huge NRE cost problem, at least for 16-12. I understand interposers with MEMs (including optics), 130 SiGe and power supply chiplets. With the huge money pouring into finFETs, and IFS opening up, I am questioning why the exotic RAM companies put effort into fdsoi. This is why I opened 2 threads simultaneously (Exotic RAM and Why FDSOI). I didn't want to put both questions into the same thread.

Yes Nish, I am pissing on France.
 
Ian, I read what you wrote. We automated the GF22 process (analog, digital P&R, stdcells) and constructed SerDes, PLLs, ADCs, bandgaps, Pclamps, etc semi-automatically. We understand how to crudely tune VCOs through switches to caps and fine tuning them by changing the depletion region. We understand how to change the threshold by controlling the back gate. We also have S parameters, etc in our environment and we have analog in our name.

My intent is to gather as many reasons why circuit designers see the NEED of using the European process (Nish, I agree with you) and ensure that we can make a functionally equivalent version on the US based processes (FinFETs). I like putting as many circuit functions onto 1 chip, and I believe the speeds of 16-12nm processes can fetch (through interleaving) and process the incoming signals such that mixers, etc are a thing of the past. There are amazing things you can put onto one chip. Digital calibration makes analog more accurate. eFPGAs, CPUs with embedded SRAM are other features that are jammed into the same chip.

We have automated finFETs, so we have solved the huge NRE cost problem, at least for 16-12. I understand interposers with MEMs (including optics), 130 SiGe and power supply chiplets. With the huge money pouring into finFETs, and IFS opening up, I am questioning why the exotic RAM companies put effort into fdsoi. This is why I opened 2 threads simultaneously (Exotic RAM and Why FDSOI). I didn't want to put both questions into the same thread.

Yes Nish, I am pissing on France.
It sounds as if for your applications there's no real advantage for 22FDX. We use it for specific purposes (*very* high-speed analog) where FinFET just hasn't got high enough Ft -- especially the PMOS -- to get the bandwidth we need, and where driving the back gate gives us a big advantage. Compared to 130nm/90nm SiGe BiCMOS (similar Ft) we can get better power efficiency for these circuits, which is also important.

But for the ADC/DAC 5nm FinFET gives a lot lower power, and integrating these with the DSP instead of being separate also saves more power -- the data rate between the converters and the DSP is about 5Tb/s...

I think your anti-EU bias is showing though... ;-)
 
No, just France :)

On the technical issue, do you see where I am headed here? Take the power hit on the SiGe, but make it up on the DUV FinFETs (EUV... fuhgeddaboudit). Add a bit more *RAM, add those horrible eFGPAs if you really have to, or possibly an equally horrible FPGA chiplet (future), add an HBM (don't overdo the SRAM).

Back to geopolitics... Dresden... sure. Made sense, but.... I speculate that is France being equal to Germany. If France leapfrogs Germany, then Germany will dish it back. They want to be the same and put up the tariffs. India will do the same on the 28nm. Japan, smart and practical as always. 28-16 hits the sweet spot, and us crazy Americans will race out to the front as always. Isn't it nice to have a printing press?

Our semiconductor industry is amazing. It is now technology, economics, politics, and military all in one.
 
No, just France :)

On the technical issue, do you see where I am headed here? Take the power hit on the SiGe, but make it up on the DUV FinFETs (EUV... fuhgeddaboudit). Add a bit more *RAM, add those horrible eFGPAs if you really have to, or possibly an equally horrible FPGA chiplet (future), add an HBM (don't overdo the SRAM).

Back to geopolitics... Dresden... sure. Made sense, but.... I speculate that is France being equal to Germany. If France leapfrogs Germany, then Germany will dish it back. They want to be the same and put up the tariffs. India will do the same on the 28nm. Japan, smart and practical as always. 28-16 hits the sweet spot, and us crazy Americans will race out to the front as always. Isn't it nice to have a printing press?

Our semiconductor industry is amazing. It is now technology, economics, politics, and military all in one.
Doesn't work for us -- we need the lowest power for the RF (22FDX) *and* the ADC/DAC/DSP (EUV 5nm FinFET)... :-(

28nm-16nm only "hits the sweet spot" for some applications -- by the sound of it, yours. Don't assume it's the same for everyone else because it's not -- otherwise Apple and Intel and AMD (and us) would still be using nice cheap easy 16nm FinFET, wouldn't we?

I'd be careful about bragging how brilliant the US semiconductor industry is -- design (which I work in too) yes, manufacturing, clearly not, which is why the US government is paying TSMC so much to set up shop there.

Also perhaps focus less on the EU subsidies to semiconductor (and plane) manufacturers, when the US is doing exactly the same or more so... ;-)

(I work in the UK for a US company, and we use foundries in Taiwan, the US and Europe -- I don't have any axes to grind, just need the best technology for the job... :)
 
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You take me a little too seriously... and of course we go with Taiwan's stuff. We ain't crazy!

I don't recall saying we were more brilliant. Don't put words in my mouth.

My goal is to keep customer's NRE below $3M (not including interposer) and on ASICs, not data center chips. Those goliaths are a different.

Perhaps we will continue to support gf22... out of Dresden :)
 
You take me a little too seriously... and of course we go with Taiwan's stuff. We ain't crazy!

I don't recall saying we were more brilliant. Don't put words in my mouth.

My goal is to keep customer's NRE below $3M (not including interposer) and on ASICs, not data center chips. Those goliaths are a different.

Perhaps we will continue to support gf22... out of Dresden :)
"...and us crazy Americans will race out to the front as always."

Your exact words... ;-)

Now you're starting to show what your priorities are -- you were asking open-ended "why would anyone use 22FDX?" questions before -- things become clearer. I think there's no doubt, for your applications something like TSMC 12FFC FinFET (16nm shrink) is a good choice, assuming the digital needs it and you can afford the mask cost, or 22nm planar (28nm shrink) if it doesn't and/or you can't.

22FDX is unlikely to be the best choice for you, even if your customers have integrated RF the Ft difference only really shows up if they're doing mmWave or radar or ultrafast optical comms -- which I doubt, going by what you've said.

For others, the choices may well be different, and that's why people might use 22FDX. Like I said, horses for courses... ;-)
 
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Absolutely we (and the gutsy TSMC and ASML) will race out in front, and I did use the word "crazy". We have the printing presses (for now, but BRICS may change that... dunno) and we will let our tax payers bear the burden. Let's get to the moon first! Personally, I think Japan has picked the sweet spot.

Note to Ian: I am being sarcastic when I say that we should have wasted taxpayer money going to the moon.
 
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It sounds as if for your applications there's no real advantage for 22FDX. We use it for specific purposes (*very* high-speed analog) where FinFET just hasn't got high enough Ft -- especially the PMOS -- to get the bandwidth we need, and where driving the back gate gives us a big advantage. Compared to 130nm/90nm SiGe BiCMOS (similar Ft) we can get better power efficiency for these circuits, which is also important.

But for the ADC/DAC 5nm FinFET gives a lot lower power, and integrating these with the DSP instead of being separate also saves more power -- the data rate between the converters and the DSP is about 5Tb/s...
I am curious, how do you see the rise of chiplets playing out here? Does it become more interesting to keep your analog on 22FDX adjacent to an N5 digital core, and will the market evolve to support specialized processes longer term via normalizing the advanced packaging?

Perhaps that adjacent path can still be analog where the N5 does not need to drive the load, have the same ESD protection, and is not operating with such a low noise requirment, so a mm or two of trace between N5 and 22FDX literally bridges their different advantages?

We already see this playing out in optics like Ayar, partly because optical gadgets are too giant to be a good use of area on a leading edge digital process, so they seem likely to settle on chiplets with optimal processes and low cost of area.
 
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