Scientific Analog, Inc. is sponsoring an IEEE TechInsider Webinar titled, “Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification.” The webinar is scheduled at 15:00-16:30 PM Pacific Time on Tuesday, June 21, 2022, and is given by Charles Dančak, an expert instructor and consultant in SystemVerilog.
This webinar focuses on how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog’s XMODEL.
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog’s XMODEL.
Using a digitally-programmable audio bandpass filter as an example, we’ll show how to write a UVM testbench that measures the filter’s transfer gain at randomly-chosen frequencies, collects the results in a scoreboard until the desired coverage is met, and checks the supply current and bias voltages during power-down with assertions. The webinar will start with an intuitive yet systematic introduction to UVM.
Resource Materials (click here to download):
- - Webinar video recording (link)
- - Webinar presentation slides
- - UVM testbench source codes
All product names contained herein are the trademarks of their respective holders.
Link to Press Release