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U.S. updates export curbs on AI chips and tools to China

Daniel Nenni

Admin
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FILE PHOTO: Illustration shows U.S. and Chinese flags

WASHINGTON (Reuters) -The Biden administration on Friday revised rules aimed at making it harder for China to access U.S. artificial intelligence (AI) chips and chipmaking tools, part of an effort to hobble Beijing's chipmaking industry over national security concerns.

The rules, released in October, seek to halt shipments to China of more advanced AI chips designed by Nvidia and others as Washington cracks down on Beijing over concerns its advancing tech sector could help boost China's military.

The new rules, which run 166 pages in length, go into effect on Thursday. They clarify, for example, that restrictions on chip shipments to China also apply to laptops containing those chips.

The Commerce Department, which oversees export controls, has said it plans to continue updating its restrictions on technology shipments to China as it seeks to bolster and fine-tune the measures.

 
So in a way, this already restricts PCs from Intel to their largest market?
I haven't been able to find a link to the actual Dept. of Commerce document, but I suspect the restriction mentioned above applies to desktops and laptops with discrete GPUs and not those with CPUs with integrated graphics cores, like the Intel Core Ultra 7 (which has eight integrated Xe cores).

Assuming my guess is correct, Intel and AMD CPU-based systems are being restricted from Chinese government use, and Intel and AMD-based systems in general with discrete GPUs are being restricted in some way from export to China. I suspect that these restrictions will only sum to a fraction of Intel's and AMD's total sales in China. I'd be quite surprised if it was more than 20%, but obviously I'm just guessing.

(It is odd that there are so many press mentions of the 166 page update to the DoC restrictions, but not one link I can find to the actual document.)
 
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I believe this report from the White House titled "Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-based Growth" is the document in question. Originally created in June 2021, it's a bit longer than 166 pages, weighing in at 250.

The first part, "Review of Semiconductor Manufacturing and Advanced Packaging", shown on pages 21-82 is what is being addressed with the Department of Commerce with regard to the revision of rules mentioned above.

In particular, page 23 (summary) and page 80 (detail) highlight recommendation #7 which aims to "Protect U.S. Technological Advantage in Semiconductor Manufacturing and Advanced Packaging."
 
I believe this report from the White House titled "Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-based Growth" is the document in question. Originally created in June 2021, it's a bit longer than 166 pages, weighing in at 250.

The first part, "Review of Semiconductor Manufacturing and Advanced Packaging", shown on pages 21-82 is what is being addressed with the Department of Commerce with regard to the revision of rules mentioned above.

In particular, page 23 (summary) and page 80 (detail) highlight recommendation #7 which aims to "Protect U.S. Technological Advantage in Semiconductor Manufacturing and Advanced Packaging."
This is the Oct 2023 release referred to in the Reuters presser:

It updates a rule from a year prior which is linked towards the end of the update.
 
Interesting.

Might well be noted footnote 40 on page 31 of the earlier (2021) document linked above,
An additional area is the ongoing development of the RISC-V open standard ISA, which provides IP open source and license-free, is a relatively new phenomenon in the microprocessor IP licensing area. Initially developed at the University of California, Berkeley in 2010 with funding from Intel, Microsoft and others, the RISC-V IP is owned and maintained by the non-profit RISC-V Foundation, founded in the United States in 2015. In December 2018, the foundation announced intentions to re-incorporate in Switzerland, in part to “alleviate uncertainty” surrounding export restrictions from the United States and the goal of “calming concerns of political disruption to the open collaboration model.” To date, RISC-V IP has not made significant inroads on the microprocessor-enabling ISA space dominated by Intel and Arm. As the RISC-V Foundation states, it does not represent “a great new chip technology,” but rather is attractive to many because it is a common and open standard. See: “History of RISC-V”,(RISC-V, 2021).
 
I believe this report from the White House titled "Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-based Growth" is the document in question. Originally created in June 2021, it's a bit longer than 166 pages, weighing in at 250.

The first part, "Review of Semiconductor Manufacturing and Advanced Packaging", shown on pages 21-82 is what is being addressed with the Department of Commerce with regard to the revision of rules mentioned above.

In particular, page 23 (summary) and page 80 (detail) highlight recommendation #7 which aims to "Protect U.S. Technological Advantage in Semiconductor Manufacturing and Advanced Packaging."
This is the Oct 2023 release referred to in the Reuters presser:

It updates a rule from a year prior which is linked towards the end of the update.
Neither one of these documents is recent enough to be news, or close to the quoted length. Interesting nonetheless.
 
Interesting.

Might well be noted footnote 40 on page 31 of the earlier (2021) document linked above,
I've been wondering about what the USG thinks about RISC-V, which "escaped" to Switzerland with the expressed purpose of skirting US IP restrictions on government funded R&D. I think the RISC-V leadership is acutely aware of the legal tightrope they're walking with the US government, and this page from their website was clearly written with a lot of professional legal help and exhibits extensive butt covering.



DARPA Influence

After the invention of RISC-V, many projects used it, including research programs funded by the Defense Advanced Research Projects Agency (DARPA), in many places and many companies. Open source standards provide great benefits to U.S. taxpayers in reducing the cost of advanced military system development, and also increases security by allowing the government to build their own trusted implementations at low cost. Note that several decades ago, the United States Air Force developed the open standard MIL-STD-1750 16-bit processor ISA for military applications for the same reasons (https://en.wikipedia.org/wiki/MIL-STD-1750A).

The UC Berkeley ASPIRE Lab succeeded the Par Lab, and was led by Krste Asanović. It lasted from 2013 to 2018 and led to the building of several RISC-V compatible microprocessors. It had funding from DARPA as well as from many companies. The DARPA funding was basic research funding (6.1 category).

Basic research funding to universities is largely for unrestricted research with permission to publically disseminate the results. This contract is the standard model for U.S. federal grants to universities, and allows for results from the funded work to be published in the open literature and made accessible to the public at large, worldwide. The government retains rights to use any technology developed in the research, but, unless explicitly stated, does not restrict the technology.

A related DARPA photonics program predates RISC-V and funded research at MIT in 2006. The research supported the development of integrated silicon photonics. Later stages of funding at MIT and Berkeley were used to build prototype chips, which included RISC-V cores as infrastructure to demonstrate the photonic links.

The ASPIRE Lab was funded by the DARPA Power Efficiency Revolution for Embedded Computing Technologies (PERFECT)program. The goal of the program was to develop revolutionary approaches as well as the technologies and techniques to provide the power efficiency required to enable embedded computing systems. Researchers used RISC-V based systems to demonstrate the ideas in that program.

In all of these funded projects, the RISC-V ISA specification and RISC-V open-source cores were not a contract deliverable. RISC-V was just the infrastructure separately developed to support the funded research.

While DARPA did not fund the original RISC-V ISA definition, DARPA funding played a significant role in its later development. The linked article on the SSITH Voting Machine and DOD presentation by Linton Salmon detail some of the areas where DARPA research continues to support RISC-V.

DARPA is currently funding a large set of programs around open-source hardware technology. RISC-V International has never had DARPA funding, nor pursued or received funding from any government.
 
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