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TSMC to charge more for U.S. made chips?

  • fighter jets use mature technology from DOD approved fabs. and TSMC hates low volume products. Are Fighter Jets using <=7nm or TSMC today?

"fighter jets use mature technology from DOD approved fabs".

Either you're talking about the DOD's Trusted Foundry program or you are talking about the "approved fabs" in general, TSMC and some other Taiwanese foundries have been in the DOD semiconductor supply chain for a while. Their names are not on the official list but their products and services are widely used. The Xilinx/AMD FPGAs used on F-35 and made in TSMC fabs in Taiwan is an example.

Looking forward TSMC Arizona N5 capability is a good resource for several critical US weapon systems under development. Those systems, such as B21, F/A-XX, and Next Generation Air Dominance (NGAD), are coming out in the next 5 to 10 years. TSMC leading edge and stable N5 technology today will certainly become not so leading edge by then. It's a good balance between performance, cost, and risk.
 
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Military and space applications typically require radiation hardening. Either by fab technology (Silicon on Insulator for example) or design (triple voting circuits, e.g.). Many time, both. There is always a premium for this, and a premium for small batches.
Housing the SIP in a lead package won't cut it?
 
Housing the SIP in a lead package won't cut it?
I'm wondering why you asked me this. From your other many posts here, you have some deep industry experience/contacts. So perhaps your query was rhetorical?

It's been a couple decades but mil/aero/space packages were all ceramic based then iirc. And the chips were rated to operate reliably from m25 to 125c. Heck, in space it may be a wider range.

There are probably some systems these days that get away with COTS chips and packages with some clever system design and redundancy in the critical places.

All these requirements come at a premium. Even lead package as you suggest (if that's actually a thing) would be a special case with its own premium.

Lets be clear, the mil/aero/space needs are small potatoes volume wise. The new US fabs have already locked in contracts with their big commercial customers as others have mentioned. The commercial requirements are just like those from overseas fabs. But the customers have already agreed to pay a higher rate to ensure a second source stateside. With hopes the stateside fabs will get cheaper over time.
 
But there is no doubt US fabs are more expensive to run than overseas ones. Otherwise, we would still have many more here. Folks should expect to pay more for US made chips and I'm sure TSM's big US customers are prepared to do so. For them it is cheap insurance (cheap because the relative volumes are low). Over time they are hoping fab learning here will allow the pricing to come down while more shells are filled. Just in case things change in Asia.
Not clear. Plants are highly automated, labor requires premium salaries everywhere and will rise in Taiwan. Land is cheap in the USA and construction in AZ seems swift. TSMC is undoubtedly very, very good and the best in the USA, Intel, had some disastrous mistakes around 2015 that it took forever to recover from. So, a one-two punch resulting in no USA fabs now at the TSMC level. This was not proof USA was too expensive.

But TSMC is noticeably Taiwan-chauvanistic, it comes up in their talk all the time and is openly cited as their strength. But it has also been a weakness - there are almost no companies that big who have never woken up to the geopolitics of gigabusiness - and people who think like that are prone not to approach other cultures looking for alternative strengths. I expect that Intel, who have been international - with USA roots - for over 40 years will actually give them a run for their money on cost effective fabs in multiple regions. And even TSMC will have staff who adapt and get the hang of being good in the USA (although they may have some difficulties with the current plan to seemingly copy-exact a Taiwanese fab design).
 
I'm wondering why you asked me this. From your other many posts here, you have some deep industry experience/contacts. So perhaps your query was rhetorical?

It's been a couple decades but mil/aero/space packages were all ceramic based then iirc. And the chips were rated to operate reliably from m25 to 125c. Heck, in space it may be a wider range.

There are probably some systems these days that get away with COTS chips and packages with some clever system design and redundancy in the critical places.

All these requirements come at a premium. Even lead package as you suggest (if that's actually a thing) would be a special case with its own premium.

Lets be clear, the mil/aero/space needs are small potatoes volume wise. The new US fabs have already locked in contracts with their big commercial customers as others have mentioned. The commercial requirements are just like those from overseas fabs. But the customers have already agreed to pay a higher rate to ensure a second source stateside. With hopes the stateside fabs will get cheaper over time.

"Lets be clear, the mil/aero/space needs are small potatoes volume wise. The new US fabs have already locked in contracts with their big commercial customers as others have mentioned."

TSMC Arizona fabs will serve both large production volume customers (like Apple, AMD, Nvidia, and Qualcomm) and small volume customers for military and national security related applications.

To support military and national security related applications is one of the original reasons to have this TSMC Arizona fab project. Those large production volume customers are making this small volume but important goal feasible.
 
I am asking about packaging because it is likely that the "chip" that the DoD wants is actually a SIP with several dies (high speed logic, HBM, etc). Perhaps it is more cost effective to focus on the packaging of the SIP/module/hybrid.

I've got 21 MSEE interns starting May 15th. Based on your timely suggestion, I will put one of them on the 2 out 3 voting latches/flops protecting the flipped bit just to say we can handle it. Sure, we will do it on GF22fdsoi too (horses for courses), but it seems to me that you are better off making 3 systems in radiation hardened packages rather than making bloated and slower die. This is just my first order opinion.

I think it was a legitimate question. Any radiation/EMI experts in this forum?
 
I think there are 2 business models, both plausibly successful in the US:
1) Operate on a Moore’s-Law basis reducing per chip cost, increasing output by shrinks that do both, which means you can operate at a profit, but at the cost of ongoing high and rising capital costs
2) Operate a fixed node for a long time, reducing cost per chip via depreciation, while using profits to invest in more capa, increasing output, which also reduces costs

Returning to TSMC AZ, that is, at this point, a type 2 fab; 1 node, disconnected from Moore’s Law, profitable but in an isolated way that isn’t comparable to fabs that bear the cost/reap the rewards of Moore’s Law.

Intel’s fabs in Chandler are type 1.

Will the CHIPs act support type 2?
 
I think there are 2 business models, both plausibly successful in the US:
1) Operate on a Moore’s-Law basis reducing per chip cost, increasing output by shrinks that do both, which means you can operate at a profit, but at the cost of ongoing high and rising capital costs
2) Operate a fixed node for a long time, reducing cost per chip via depreciation, while using profits to invest in more capa, increasing output, which also reduces costs

Returning to TSMC AZ, that is, at this point, a type 2 fab; 1 node, disconnected from Moore’s Law, profitable but in an isolated way that isn’t comparable to fabs that bear the cost/reap the rewards of Moore’s Law.

Intel’s fabs in Chandler are type 1.

Will the CHIPs act support type 2?

If I understand the two business models you summarized correctly, TSMC are in both business models for its current and future US fabs.

On the other hand Intel's Arizona and future Ohio fabs are in both models too. It's because Intel's IDM 2.0 and IFS business strategies require Intel to do so.

In terms of Chip Act subsidiaries, I believe it will cover both models for practical reasons.
 
If I understand the two business models you summarized correctly, TSMC are in both business models for its current and future US fabs.

On the other hand Intel's Arizona and future Ohio fabs are in both models too. It's because Intel's IDM 2.0 and IFS business strategies require Intel to do so.

In terms of Chip Act subsidiaries, I believe it will cover both models for practical reasons.
Two things to notice:
1) Samsung Austin was and is a single node fab, 14nm, from 2013 to present
2) Meanwhile Samsung type 1 fabs moved to 10nm, 7nm, 5nm, and 3nm

Skipping that may nodes isn’t accidental, it’s a different business model.

I’m calling that type 2, and positing TSMC will do the same in AZ, most likely, based on their comments. TSMC AZ will not be leading edge, even initially, 5nm will be more of a trailing edge, volume mature node by 2025. But 5nm could be a good node for type 2.
 
Two things to notice:
1) Samsung Austin was and is a single node fab, 14nm, from 2013 to present
2) Meanwhile Samsung type 1 fabs moved to 10nm, 7nm, 5nm, and 3nm

Skipping that may nodes isn’t accidental, it’s a different business model.

I’m calling that type 2, and positing TSMC will do the same in AZ, most likely, based on their comments. TSMC AZ will not be leading edge, even initially, 5nm will be more of a trailing edge, volume mature node by 2025. But 5nm could be a good node for type 2.
I'm thinking 3nm would be a better stopping place for a long term node, being the last FinFET. Kind of another 28 nm node in that sense (yes, there was a 20nm, but it sucked).
 
I'm thinking 3nm would be a better stopping place for a long term node, being the last FinFET. Kind of another 28 nm node in that sense (yes, there was a 20nm, but it sucked).
That's what TSMC CEO C.C Wei said. "important and long lasting node"
 
I've got 21 MSEE interns starting May 15th. Based on your timely suggestion, I will put one of them on the 2 out 3 voting latches/flops protecting the flipped bit just to say we can handle it. Sure, we will do it on GF22fdsoi too (horses for courses), but it seems to me that you are better off making 3 systems in radiation hardened packages rather than making bloated and slower die. This is just my first order opinion.

I think it was a legitimate question. Any radiation/EMI experts in this forum?
Space radiation is not blocked by lead - that works for X-rays, where the dense electron clouds with high-voltage inner orbitals do the work. Radiation from space is stronger stuff, needs nucleii and light elements give you a higher blocking ratio per weight, but it varies a lot since some nucleii love to participate in some reactions, while others do not. But up in space it is mostly just high energy protons (ranging up to absurd energy) so water and plastic (all that hydrogen) are best ratio. But not nearly practical in thickness, mostly. It gets nicely effective at a meter thick.

In practice, your circuit has to live with it. Which means firstly, do not suffer permanent damage. Don't have weak crystals and don't include features prone to avalanche damage when a particle drills through an insulator or a channel that is supposed to be off. This is why specific processes and materials are preferred. They still have glitches, just not permanent ones. Over a decade or so the radiation will add up to permanent damage, but you want a reasonably long life until then.

As for the glitches, which are hopefully just soft errors, you want to detect them. SRAM is easy, SECDED parity should solve it, along with regular sweeps to write back corrections and avoid accumulating dual errors. Busses should have SECDED, too. DRAM is surprisingly good due to its large capacitor size, it has much lower radiation fault rate per bit than SRAM, but there are lots of bits, and the same recipe -ECC and regular sweeps writing back the corrections. I do not offhand know what happens to Flash, but it is likely you want to stick with SLC or MLC for margins and then apply the same sweep strategy.

Which pretty much leaves the logic. There is some progress in using modular checksums within a core, this is what IBM does on its POWER mainframes, so for example a multiply or divide is designed in IP blocks which self-check at some tradeoff for overhead vs. detection ratio. I don't know if that kind of IP is available. I have never heard of anyone building voting circuits down to the gate level. Usually voting is done at a higher level. For most purposes duplication with retry is acceptable, because the dominant fault modes are transient (if you have the right process and material to survive the years needed). Triplicate can be needed for real time.

Just as you say, it is cheaper to replicate whole sub-assemblies because then each of them will have best case performance and low cost.
 
* how does a data center guy know this?

Well, I needed to see what we might need to do with data centers in high altitude cities, where radiation can be 10x higher. So I studied the subject for a while. One of the best things for a data center would be to put a thick borax-infused concrete roof on it. But that is specific to avoiding neutrons from cosmic rays in the atmosphere, not useful in space.
 
Which pretty much leaves the logic. There is some progress in using modular checksums within a core, this is what IBM does on its POWER mainframes,
Just a small nitpick, POWER chips are not used in mainframes. They do make servers with them, and I believe they emulate the old AS/400 minicomputers as well as run AIX, but mainframes use their own processors. Again, just a small point, not really important.
 
Two things to notice:
1) Samsung Austin was and is a single node fab, 14nm, from 2013 to present
2) Meanwhile Samsung type 1 fabs moved to 10nm, 7nm, 5nm, and 3nm

Skipping that may nodes isn’t accidental, it’s a different business model.

I’m calling that type 2, and positing TSMC will do the same in AZ, most likely, based on their comments. TSMC AZ will not be leading edge, even initially, 5nm will be more of a trailing edge, volume mature node by 2025. But 5nm could be a good node for type 2.

I would bet TSMC AZ will be N4x and N3x which are not far apart in regards to PPA. So yes AZ will be leading edge. Since Apple has a special recipe bleeding edge N3 I don't think Apple chips will be made in AZ even though Tim Cook said otherwise.
 
Good stuff Tanj. I am going to keep these notes. Thanks!

We can construct voting flops. Why not? Next year is an election year.
 
Which pretty much leaves the logic. There is some progress in using modular checksums within a core, this is what IBM does on its POWER mainframes, so for example a multiply or divide is designed in IP blocks which self-check at some tradeoff for overhead vs. detection ratio. I don't know if that kind of IP is available. I have never heard of anyone building voting circuits down to the gate level. Usually voting is done at a higher level. For most purposes duplication with retry is acceptable, because the dominant fault modes are transient (if you have the right process and material to survive the years needed). Triplicate can be needed for real time.
Just curious, is it really the logic that suffers from radiation, or more precisely a flip-flop/latch that samples the value of logic at a single point in time? My naive expectation would be the latter: if an output signal is based on combinational logic that is a function of its inputs, then any deviation from its normal output is temporary.
 
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