TSMC reportedly building 1nm chip fab in northern Taiwan

[Daniel Nenni]

Semiconductor giant keeps investing in Taiwan for advanced process node chips​

By Huang Tzu-ti, Taiwan News, Staff Writer
2022/10/31 11:41

This photo shows the icon of TSMC (Taiwan Semiconductor Manufacturing Company) during the Taiwan Innotech Expo at the World Trade Center in Taipei, Ta... (AP photo)
TAIPEI (Taiwan News) — Taiwan Semiconductor Manufacturing Company (TSMC) is reportedly planning a 1 nanometer fab in Taoyuan.

The proposed plant will be located in an industrial park in Longtan District, operated by the Hsinchu Science Park (HSP), wrote Commercial Times on Monday (Oct. 31).
The report cited sources as saying that the support from HSP and the fact that TSMC is already running two semiconductor packaging and testing factories at the Longtan tech park make it an ideal place for 1nm chip production.

The world’s largest contract chipmaker did not deny or confirm the report, saying only that it does not rule out any possibility. It added that it will continue to invest in advanced chip manufacturing in Taiwan, per CNA.

TSMC’s 3nm chips will enter mass production in the fourth quarter and account for about 4% to 6% of its total output next year. An upgraded version of its 3nm chips (N3E) is expected to start commercial production in the second half of 2023, said CNA.

Mass production of the eagerly anticipated 2nm chips is likely by 2025 at HSP’s Baoshan facility in Hsinchu. The 2nm chips are touted as allowing for 10% to 15% faster computing speed and using 25% to 30% less power compared to the company's 3nm silicon.

TSMC reportedly building 1nm chip fab in northern Taiwan | Taiwan News | Oct. 31, 2022 11:41

www.taiwannews.com.tw

 

[nghanayem]

Does anyone know how TSMC's R&D and ramps even work? Does TSMC have some lab where they work on the node from a low volume, and then when it is ready to be made manufacturable it is sent to the initial fab that will be making it, and that fab will gradually ramp it as the node becomes more production ready? Or do they do something similar to intel with Hillsboro and have all R&D and initial ramp done at one facility; from there sending it to their first HVM fab for that node and moving on to TSMC's next node? Does Samsung foundry function in a similar manner to TSMC (with the difference being that the lab phase partially being done by IBM)?

 

[blueone]

Does anyone know how TSMC's R&D and ramps even work? Does TSMC have some lab where they work on the node from a low volume, and then when it is ready to be made manufacturable it is sent to the initial fab that will be making it, and that fab will gradually ramp it as the node becomes more production ready? Or do they do something similar to intel with Hillsboro and have all R&D and initial ramp done at one facility; from there sending it to their first HVM fab for that node and moving on to TSMC's next node? Does Samsung foundry function in a similar manner to TSMC (with the difference being that the lab phase partially being done by IBM)?

I suspect TSMC works a lot like Intel, but I can't find any evidence.

 

[hist78]

Does anyone know how TSMC's R&D and ramps even work? Does TSMC have some lab where they work on the node from a low volume, and then when it is ready to be made manufacturable it is sent to the initial fab that will be making it, and that fab will gradually ramp it as the node becomes more production ready? Or do they do something similar to intel with Hillsboro and have all R&D and initial ramp done at one facility; from there sending it to their first HVM fab for that node and moving on to TSMC's next node? Does Samsung foundry function in a similar manner to TSMC (with the difference being that the lab phase partially being done by IBM)?

I believe Fab 12B and facility in Longtan (for advanced packaging) are their major R&D sites.

https://www.tsmc.com/english/aboutTSMC/TSMC_Fabs

 

[VCT]

 

[VCT]

Does anyone know how TSMC's R&D and ramps even work? Does TSMC have some lab where they work on the node from a low volume, and then when it is ready to be made manufacturable it is sent to the initial fab that will be making it, and that fab will gradually ramp it as the node becomes more production ready? Or do they do something similar to intel with Hillsboro and have all R&D and initial ramp done at one facility; from there sending it to their first HVM fab for that node and moving on to TSMC's next node? Does Samsung foundry function in a similar manner to TSMC (with the difference being that the lab phase partially being done by IBM)?

Yes, TSMC 3nm R&D team moved on to 1.4nm in April or May. That means 3nm R&D is successfully finished and MP team will take over 3nm for mass production.　

 

[Daniel Nenni]

TSMC Fab 12 in Hsinchu is for R&D, it is then rolled out to the target fabs. Intel does the same in OR with their copy exact methodology.

 

[blueone]

TSMC Fab 12 in Hsinchu is for R&D, it is then rolled out to the target fabs. Intel does the same in OR with their copy exact methodology.

As I suspected. Cut off the fabs outside of Taiwan from the Taiwan R&D centers, and most of the advantages of the overseas fabs are lost. Correct?

 

[nghanayem]

As I suspected. Cut off the fabs outside of Taiwan from the Taiwan R&D centers, and most of the advantages of the overseas fabs are lost. Correct?

I suppose in theory they can run the process just fine without them once they get ramped. In practice things would be very rough as there would be alot of confusion in the short term.

 

[Daniel Nenni]

As I suspected. Cut off the fabs outside of Taiwan from the Taiwan R&D centers, and most of the advantages of the overseas fabs are lost. Correct?

The TSMC fab in AZ is 5nm which is a finished node, no R&D required.

 

[Sherlock]

News saying AZ fab will run 3nm, is this true?

 

[VCT]

News saying AZ fab will run 3nm, is this true?

Not as for current plan. 5nm AZ fab will MP in 2024. Maybe 3nm will be available in 2027-2027. But no announcement yet.

 

[Daniel Nenni]

News saying AZ fab will run 3nm, is this true?

Link?

The AZ facility is quite big so TSMC could add 3nm but the initial launch will be 5nm.

 

[Sherlock]

台積美國廠 將切入3奈米 | 聯合新聞網

台積電在美國亞利桑那州設立的十二吋晶圓廠下月舉行「首部機台移機」典禮，台積電供應鏈指出，台積電美國廠未來將會切入三奈米，...

udn.com

Supply chain rumors saying "in the future" AZ fab will add 3nm beside 5nm. If 3nm is "the" big node, then surely this is reasonable.

擬在美國加碼蓋3奈米廠 台積電回應了 - 工商時報

晶圓代工龍頭台積電美國亞利桑那州5奈米廠將於2024年量產，媒體報導台積電評估投資興建第2座晶圓廠。台積電表示，不回應市場傳聞。

ctee.com.tw

TSMC official response as usually " not responding to rumors" .

 

[Daniel Nenni]

台積美國廠 將切入3奈米 | 聯合新聞網

台積電在美國亞利桑那州設立的十二吋晶圓廠下月舉行「首部機台移機」典禮，台積電供應鏈指出，台積電美國廠未來將會切入三奈米，...

udn.com

Supply chain rumors saying "in the future" AZ fab will add 3nm beside 5nm. If 3nm is "the" big node, then surely this is reasonable.

擬在美國加碼蓋3奈米廠 台積電回應了 - 工商時報

晶圓代工龍頭台積電美國亞利桑那州5奈米廠將於2024年量產，媒體報導台積電評估投資興建第2座晶圓廠。台積電表示，不回應市場傳聞。

ctee.com.tw

TSMC official response as usually " not responding to rumors" .

TSMC N3 will be a larger node than N5 so US expansion is reasonable. It would also make it easier for Intel since they will use TSMC N3 and the fabs are close . If you are in AZ it is worth a drive by the TSMC site. It is MASSIVE! 20+ cranes! Rumor has it there will be a ribbon cutting event in AZ next month. Stay tuned.

 

[nghanayem]

TSMC N3 will be a larger node than N5 so US expansion is reasonable. It would also make it easier for Intel since they will use TSMC N3 and the fabs are close . If you are in AZ it is worth a drive by the TSMC site. It is MASSIVE! 20+ cranes! Rumor has it there will be a ribbon cutting event in AZ next month. Stay tuned.

Is proximity to intel relevant? Most of their advanced packaging is in SE Asia (Utah is the sole exception to this and my understanding is that it is small).

 

[Mooredaddy]

I keep seeing so many badly sourced articles about 3nm orders being cut at TSMC while management is adamant that 3nm is going to be a bigger node then 5nm. I highly suspect these articles are wrong but where do they keep coming from? Is someone trying to manipulate the market or what’s going on here? Any thoughts Daniel and others?

 

[Daniel Nenni]

I keep hearing so many badly sourced articles about 3nm orders being cut at TSMC while management is adamant that 3nm is going to be a bigger node then 5nm. I highly suspect these articles are wrong but where do they keep coming from? Is someone trying to manipulate the market or what’s going on here? Any thoughts Daniel and others?

N3 will be the last FinFET process at TSMC, there are more design starts for N3 than N5 at this stage in a process, N2 will be a yield learning node. So, in my opinion, N3 will be the biggest node in the history of TSMC, absolutely.

 

[nghanayem]

I keep seeing so many badly sourced articles about 3nm orders being cut at TSMC while management is adamant that 3nm is going to be a bigger node then 5nm. I highly suspect these articles are wrong but where do they keep coming from? Is someone trying to manipulate the market or what’s going on here? Any thoughts Daniel and others?

If memory serves alot of this crap is coming from Daniels favorite “editorial” trendforce. It would seem their goal is to say everything is failing or low yield in an effort to farm clicks. After all it seems like bad news gets more traffic than good news.

 

[nghanayem]

N3 will be the last FinFET process at TSMC, there are more design starts for N3 than N5 at this stage in a process, N2 will be a yield learning node. So, in my opinion, N3 will be the biggest node in the history of TSMC, absolutely.

Really; bigger than 28nm?! That’s hard to comprehend with all of the people that are dropping out of the leading edge due to wafer and design costs. I guess people have overstated the issue. Alternatively this could be because at N3 TSMC is sucking away business from the other two members of the big three/TSMC has no compilation from the other planar fabs.