Surely everyone saw this coming right? This is a key reason why chiplets are such a good idea. Offload SRAM which has been scaling horribly for years now. Can even use a cheaper process on the SRAM. Monolithic dies are an endangered species (my opinion).
They will be here for cost sensitive chips for a very long time. A friend of mine worked on an idea to do cheap, cheap die stacking solution for MCUs which didn't involve TSVs exactly to allow them to use off-chip SRAM/eFLASH, which got ridiculously expensive on old nodes because of the need to run WiFi/Bluetooth stacks in software.
Nothing came out of it, not because of tech infeasibility, but lack of interest.
Few MBs cache is ok on <16nm, but are disasters on even not so old legacy nodes.
Similarly, eFLASH taking space on expensive nodes are disasters.
The expense of co-packaged SRAM is not so big for MCU makers yet, but is for CPU makers which nevertheless have much fatter profit margins. I am puzzled.
I guess the off-die L3 of AMD is a test for much, much bigger SRAMs, rather than them trying to reduce cost of current L3 sizes.
Last edited: