TSMC’s 3nm Output Could Reach Up To 100,000 Wafers Monthly By The End of 2023, As It Expects Huge Demand For Apple’s iPhone 15

[Daniel Nenni]

This year, Apple will unveil the first 3nm SoC mass manufactured on TSMC’s next-generation node, which is the A17 Bionic, and it is said to be exclusively found in the iPhone 15 Pro and iPhone 15 Pro Max. Anticipating huge demand for the newer iPhones, a report states that the Taiwanese chip giant will ramp up 3nm production by the end of this year, bringing its monthly output to 100,000 wafers.

TSMC is slowly increasing its 3nm capacity, with a report published on Economic Daily News stating that the output will reach between 90,000-100,000 monthly wafers to meet demand. The majority of the capacity is dedicated towards the A17 Bionic that will be found in the iPhone 15 Pro and iPhone 15 Pro Max, but the latest information did not mention the percentage of orders that will be fulfilled for Apple.

However, an earlier report stated that the Cupertino tech behemoth had secured 90 percent of TSMC’s 3nm chip shipments, so if that monthly wafer output reaches 100,000 units, 90,000 of them will be for Apple. The company’s competitors are refraining from taking advantage of the cutting-edge 3nm process due to the high wafer cost, and it is likely that Apple will also have to absorb these expenses.

However, TSMC can grant a concession if its output figure reaches 100,000 monthly wafers by the end of 2023, but those initial price increases can mean that the iPhone 15 Pro and iPhone 15 Pro Max will be more costly to consumers than their direct predecessors. Fortunately, there appears to be a cost-reduction solution, and that is TSMC shifting from its N3B process to N3E, but one rumor alleges that making a switch will result in the A17 Bionic losing its performance for some reason.

Foxconn is already reported to begin mass production of the iPhone 15 Pro and iPhone 15 Pro Max later this month, with an initial shipments target of 85-90 million units. Depending on demand, both TSMC and Foxconn are expected to ramp up production. However, given that the ‘Pro’ models will ship with more exclusive upgrades than the iPhone 14 Pro and iPhone 14 Pro Max, both of Apple’s supply chain partners will likely be ready for this shift in momentum.

News Source: Economic Daily News

Apple To Gain An Unrivaled Foothold Against Competitors As It Secures 90 Percent Of TSMC’s 3nm Shipments

For future iPhones, Macs, iPads, Apple is way ahead of the competition as it has reportedly obtain 90 percent of TSMC’s 3nm chip shipments

wccftech.com

 

[Daniel Nenni]

Just a couple of corrections:

"TSMC is slowly increasing its 3nm capacity"

TSMC is not slowly increasing 3nm capacity. TSMC is Quickly increasing N3 capacity. It may seem slow to outsiders but to insiders the N3 build is doing quite well. As I have said before, TSMC N3 will break records inside the FinFET family of process technologies, absolutely!

"The company’s (Apple) competitors are refraining from taking advantage of the cutting-edge 3nm process due to the high wafer cost, and it is likely that Apple will also have to absorb these expenses."

Complete nonsense. Apple gets first access to a custom version of TSMC's processes. This is part of the "most favored nation" deal that Apple cut with TSMC starting at 20nm (iPhone 6). The Apple/TSMC relationship will go down in history as one of the most successful partnerships the semiconductor foundry business has ever seen. The iPhone 6 released in September of 2014 was the first iPhone to include an Apple/TSMC jointly developed SoC so this relationship is 10+ years old and running strong.

The Apple/TSMC partnership was very disruptive and changed the face of the semiconductor industry to where we are today, with TSMC leading semiconductor manufacturing and industry behemoths like Intel and Samsung seemingly stumbling behind.

"Fortunately, there appears to be a cost-reduction solution, and that is TSMC shifting from its N3B process to N3E, but one rumor alleges that making a switch will result in the A17 Bionic losing its performance for some reason."

Complete nonsense in all regards.

The best way to get wafer price reductions is for there to be competition. Intel and Samsung must step up and make some competitive wafers.

Bottom line: From what I read and hear inside the ecosystem this will be a big year for iPhone upgrades so TSMC should see a nice N3 surge this year and next, my opinion.

As an aside, I buy a new iPhone every year and will upgrade to the iPhone 15 Pro Max. Not only do I use the phone for work, I use it for navigation and communication while sailing. Yes I have radar and a plotter but with my iPhone I have access to more weather and navigational resources. I have (2) VHF radios but the iPhone is more direct when accessing emergency services other than the Coast Guard. And yes I use the iPhone for work while sailing. It is also a great WiFi hub for other devices. I sail mostly in the San Francisco Bay but even when I go up and down the California coast I still get a signal and it keeps getting stronger with the new iPhones. Seriously, I would not sail without one and I also take my iPad Pro just in case.

 

[nghanayem]

Isn't a "fast" ramp to be expected? TSMC's plans/tool orders for fab18 were locked in years ago when they were seeing the mountain of prepayments coming in. If for the sake of argument we take N3 as being ~6mo late and that had N3 not had whatever issues it had, we would have seen N3 iPhones in late 2022; then TSMC ramping to 100k WSPM in 2023 seems like the capacity is coming online per TSMC's original schedule (ie having huge volumes a year after the lead product to accommodate the tier 2 customers moving off of N5 family). Otherwise I more or less agree with your analysis Dan (minus the point of N3E's process simplifications not being an excellent way to drive down wafer costs over N3 family).

 

[Daniel Nenni]

Isn't a "fast" ramp to be expected. TSMC's plans for fab18 were locked in years ago when they were seeing the mountain of prepayments coming in. If for the sake of argument we take N3 as being ~6mo late and that had N3 not had whatever issues it had, we would have seen N3 iPhones in late 2022; then TSMC ramping to 100k WSPM in 2023 seems like the capacity is coming online per TSMC's original schedule. Otherwise I more or less agree with your analysis Dan (minus the point of N3E's process simplifications not being an excellent way to drive down wafer costs of the N3 family).

Okay, I took "slowly increasing capacity" differently. I did not consider the N3 delay.

And you are right, N3E uses less EUV layers than N3 so there will be a manufacturing cost reduction but Apple will not use N3E. They will get an Apple specific version for their next generation of iPhones. We can all call it N3E but it is an optimized version of N3E specifically for Apple and I seriously doubt Apple will see a wafer cost reduction. And I can assure you Apple will not be losing performance.

 

[nghanayem]

On cost I was more so talking about for the non apple "peasants" of the world. As apple is a special case as they are not the ones who will run most of the wafers across N3 family's (or more specifically N3E family's) presumably loooooooong lifetime. We definitely agree on the performance front, as that would entail TSMC literally lying about N3E. Physics wise the relaxed dimensions also have performance benefits, so having worse performance than N3 (and by extension N4P) would be quite the perplexing outcome. Nerd speak for: A performance regression is not going to happen N3E will have good performance and power characteristics. I suspect that whomever wrote such a thing saw the relaxed density and assumed that meant lower performance because they don't know any better. Journalism at it's finest that statement is.

 

[IanD]

N3E doesn't have lower performance than N3 (which Apple are the only volume user of) but it does have lower density, because some of the design rules were relaxed to "increase process window" -- it seems TSMC did a mini-Intel and pushed N3 a bit too hard, then realized they needed to back off for mass production for most customers (except Apple) to avoid the risk of bad lots with process shift.

Apple don't care because their N3 volumes and product margins are so massive so they can afford to throw occasional N3 lots away, and it's a price they're willing to pay to be first in 3nm -- but TSMC presumably don't want the resulting hassle with huge numbers of customers who are may be more price-sensitive and less understanding, hence N3E (and N3P and N3X...).

The lower density on N3E means chips are bigger than N3 but the bigger process window and fewer EUV masks probably means the yielded good die cost will be similar to N3, maybe even lower. There's no performance or power hit because lower gate density means the interconnects are a bit longer but also a bit lower capacitance per um length, so the two balance out.

 

[nghanayem]

it seems TSMC did a mini-Intel and pushed N3 a bit too hard, then realized they needed to back off for mass production for most customers (except Apple) to avoid the risk of bad lots with process shift.

I do think there are a lot of similarities with N3 and 14nm. However I disagree with the above point. It is very clear the DD's are now fine. Considering N3E isn't supposed to be ready until the 2H23, I wouldn't even be surprised if N3E had worse DDs than N3 currently does. When I see N3E and TSMC's statements around this whole endeavor, my mind draws different conclusions. Given the fewer process steps N3E will have a lower DD floor than N3, and without a doubt that is part of the story. I'm sure the extra performance is also no small part of the reason TSMC is doing this. N3 being anywhere from a regression to single digit improvement over N4P (depending on if you compare the 2-1 or 2-2 library to N4P's HD) kills a key part of the value proposition of moving to a new node.

But I think the factor that with the largest impact might well be the cost and cycle time improvements inherent to N3E. Let's say as an example that an N3E wafer is 10% cheaper and 10% less dense. Combine this with lower DDs and better performance, and N3E is a no brainier. This is also beneficial for trailing edge customers (mobile too) where ASPs are small and you need to have the best cost per FET. Cycle time is also a well known critical metric for foundries. Customers want their product ASAP. The final knock on effect of this, is that it would allow TSMC to get more wafers from the same amount of tools/fab space.

 

[Xebec]

As an aside, I buy a new iPhone every year and will upgrade to the iPhone 15 Pro Max. Not only do I use the phone for work, I use it for navigation and communication while sailing. Yes I have radar and a plotter but with my iPhone I have access to more weather and navigational resources. I have (2) VHF radios but the iPhone is more direct when accessing emergency services other than the Coast Guard. And yes I use the iPhone for work while sailing. It is also a great WiFi hub for other devices. I sail mostly in the San Francisco Bay but even when I go up and down the California coast I still get a signal and it keeps getting stronger with the new iPhones. Seriously, I would not sail without one and I also take my iPad Pro just in case.

Clearly a standard use case for iPhone users ;-)

 

[IanD]

I do think there are a lot of similarities with N3 and 14nm. However I disagree with the above point. It is very clear the DD's are now fine. Considering N3E isn't supposed to be ready until the 2H23, I wouldn't even be surprised if N3E had worse DDs than N3 currently does. When I see N3E and TSMC's statements around this whole endeavor, my mind draws different conclusions. Given the fewer process steps N3E will have a lower DD floor than N3, and without a doubt that is part of the story. I'm sure the extra performance is also no small part of the reason TSMC is doing this. N3 being anywhere from a regression to single digit improvement over N4P (depending on if you compare the 2-1 or 2-2 library to N4P's HD) kills a key part of the value proposition of moving to a new node.

But I think the factor that with the largest impact might well be the cost and cycle time improvements inherent to N3E. Let's say as an example that an N3E wafer is 10% cheaper and 10% less dense. Combine this with lower DDs and better performance, and N3E is a no brainier. This is also beneficial for trailing edge customers (mobile too) where ASPs are small and you need to have the best cost per FET. Cycle time is also a well known critical metric for foundries. Customers want their product ASAP. The final knock on effect of this, is that it would allow TSMC to get more wafers from the same amount of tools/fab spac

All of which is why TSMC have pushed everyone except Apple onto N3E not N3 -- their stated reason for this was "improved process margin", and having seen both sets of design rules I can understand that, there are some significant changes.

Defect density (DD) is not the issue, N3 and N3E are similar (I've seen the curves) -- "process margin" means how much the process (usually lithography/etching) can deviate from nominal before the performance or yield takes a dive, it's how much "wiggle room" there is -- and N3 clearly didn't have enough, especially on some critical EUV layers where the biggest changes are (e.g. going from double to single patterning). Nothing like as bad as the problems intel had with 10nm where they really pushed the tools and had to basically scrap the original process and make massive changes, but a much smaller version of this -- hence the "mini-Intel" comment.

TSMC were obviously not comfortable with rolling out a process to many customers which was balanced on a production knife-edge, especially when it needs to expand to multiple fab lines to keep up with demand -- cycle time for N3E is a teeny bit faster and mask cost is a little cheaper, but these are not the things driving the switch. Introducing N3E was the right decision for a process which is going to have a huge number of high-volume customers.

 

[nghanayem]

Defect density (DD) is not the issue, N3 and N3E are similar (I've seen the curves) -- "process margin" means how much the process (usually lithography/etching) can deviate from nominal before the performance or yield takes a dive, it's how much "wiggle room" there is -- and N3 clearly didn't have enough, especially on some critical EUV layers where the biggest changes are (e.g. going from double to single patterning). Nothing like as bad as the problems intel had with 10nm where they really pushed the tools and had to basically scrap the original process and make massive changes, but a much smaller version of this -- hence the "mini-Intel" comment.

I agree with you that the DDs on N3 are healthy (TSMC has said as much themselves). Hearing that N3E is already matched is interesting to hear though. I would have assumed N3 was a bit ahead. My comment on a lower DD floor is directly related to the increased process margin. My point was that eventually there is a limit to how low TSMC can get the DD before all the remaining defects are due to random variation from EPE/process margin. Having fewer process steps and having a wider margin at these steps will remove opportunities for these random errors to happen in the first place, and by extension reduce where the bottom of their DD learning curve lies.

TSMC were obviously not comfortable with rolling out a process to many customers which was balanced on a production knife-edge, especially when it needs to expand to multiple fab lines to keep up with demand -- cycle time for N3E is a teeny bit faster and mask cost is a little cheaper, but these are not the things driving the switch. Introducing N3E was the right decision for a process which is going to have a huge number of high-volume customers.

I totally agree with you on N3E being a no-brainer for TSMC. It is simply a superior foundry process. I still disagree on a small improvement to wafer cost and cycle time not being significant. When we are talking billions of wafers across the decades long lifetimes of these fabs even saving "a measly" couple of percent on cycle time or utilities/chems cost can add up real fast. Just to illustrate my point say wafers are sold for 15k a pop, and N3E can boost TSMC's margin at that price by 1%. Additionally let's say that TSMC goes to 150k WSPM on N3 family to be conservative. That's nearly 3 billion dollars over 10 years. If one were to do a more advanced calculation you would also see this lower process cost being more important after fab assets finish their depreciation and commodities costs begin to dominate overall wafer cost.

 

[IanD]

I agree with you that the DDs on N3 are healthy (TSMC has said as much themselves). Hearing that N3E is already matched is interesting to hear though. I would have assumed N3 was a bit ahead. My comment on a lower DD floor is directly related to the increased process margin. My point was that eventually there is a limit to how low TSMC can get the DD before all the remaining defects are due to random variation from EPE/process margin. Having fewer process steps and having a wider margin at these steps will remove opportunities for these random errors to happen in the first place, and by extension reduce where the bottom of their DD learning curve lies.


I totally agree with you on N3E being a no-brainer for TSMC. It is simply a superior foundry process. I still disagree on a small improvement to wafer cost and cycle time not being significant. When we are talking billions of wafers across the decades long lifetimes of these fabs even saving "a measly" couple of percent on cycle time or utilities/chems cost can add up real fast. Just to illustrate my point say wafers are sold for 15k a pop, and N3E can boost TSMC's margin at that price by 1%. Additionally let's say that TSMC goes to 150k WSPM on N3 family to be conservative. That's nearly 3 billion dollars over 10 years. If one were to do a more advanced calculation you would also see this lower process cost being more important after fab assets finish their depreciation and commodities costs begin to dominate overall wafer cost.

N3 and N3E DD matches at the same process maturity, not the same date... ;-)

DD nowadays is largely driven by stochastic errors (shorts/opens) or particulates, and for a centered process these will be similar for N3 and N3E. The process margin issue is that if this is too small (e.g. very tight metal pitch) -- and it's pretty small for 3nm! -- a tiny bit of under/over-etching leads to a massive increase in the number of shorts/opens and a yield crash for that wafer/lot, which only shows up when you start to look at how robust the process is to things like small line/fab differences.

It's reputedly what IBM were very bad at -- great at squeezing high performance out of a process, terrible at making it repeatably and with reliable yield in mass production, but then if you only need a few mainframe CPUs where cost doesn't matter, who cares?

I didn't say that lower cost and cycle time weren't a good thing (because they obviously are) or insignificant, just that they weren't the big reason driving the change from N3 to N3E, process margin was. That's what TSMC told us... ;-)

 

[hist78]

"It's reputedly what IBM were very bad at -- great at squeezing high performance out of a process, terrible at making it repeatably and with reliable yield in mass production, but then if you only need a few mainframe CPUs where cost doesn't matter, who cares?"

For whatever reason IBM doesn't disclose its mainframe business revenue and unit sold data in recent years (please correct me if I'm wrong). IBM mainframe business is under IBM's "Infrastructure" category and it does disclose revenue for "Infrastructure" category. Although mainframes just one of several business under this category.

For Q1 2023:

• Infrastructure — revenues of $3.1 billion, down 3.7 percent, up 0.1 percent at constant currency:
  - Hybrid Infrastructure up 1 percent, up 4 percent at constant currency:
  -- z Systems up 7 percent, up 11 percent at constant currency
  -- Distributed Infrastructure down 3 percent, flat at constant currency
  - Infrastructure Support down 9 percent, down 4 percent at constant currency
  
• Source: https://newsroom.ibm.com/2023-04-19-IBM-RELEASES-FIRST-QUARTER-RESULTS

If we assume 70% of the Infrastructure revenue is generated by mainframe sales and average price for each IBM mainframe computer is at $3 million. That means IBM sold 723 units of mainframe in Q1 2023 ( ($3.1 billion * 70%) / $3 million). This is an overly simplified calculation but you can get the idea that IBM mainframe sales is really limited in terms of unit volume. Consequently IBM only needs a small quantity of processors yearly for building mainframe computers, probably less than 20,000 units a year. This is really a small number.

 

[Fred Stein]

Just a couple of corrections:

"TSMC is slowly increasing its 3nm capacity"

TSMC is not slowly increasing 3nm capacity. TSMC is Quickly increasing N3 capacity. It may seem slow to outsiders but to insiders the N3 build is doing quite well. As I have said before, TSMC N3 will break records inside the FinFET family of process technologies, absolutely!

"The company’s (Apple) competitors are refraining from taking advantage of the cutting-edge 3nm process due to the high wafer cost, and it is likely that Apple will also have to absorb these expenses."

Complete nonsense. Apple gets first access to a custom version of TSMC's processes. This is part of the "most favored nation" deal that Apple cut with TSMC starting at 20nm (iPhone 6). The Apple/TSMC relationship will go down in history as one of the most successful partnerships the semiconductor foundry business has ever seen. The iPhone 6 released in September of 2014 was the first iPhone to include an Apple/TSMC jointly developed SoC so this relationship is 10+ years old and running strong.

The Apple/TSMC partnership was very disruptive and changed the face of the semiconductor industry to where we are today, with TSMC leading semiconductor manufacturing and industry behemoths like Intel and Samsung seemingly stumbling behind.

"Fortunately, there appears to be a cost-reduction solution, and that is TSMC shifting from its N3B process to N3E, but one rumor alleges that making a switch will result in the A17 Bionic losing its performance for some reason."

Complete nonsense in all regards.

The best way to get wafer price reductions is for there to be competition. Intel and Samsung must step up and make some competitive wafers.

Bottom line: From what I read and hear inside the ecosystem this will be a big year for iPhone upgrades so TSMC should see a nice N3 surge this year and next, my opinion.

As an aside, I buy a new iPhone every year and will upgrade to the iPhone 15 Pro Max. Not only do I use the phone for work, I use it for navigation and communication while sailing. Yes I have radar and a plotter but with my iPhone I have access to more weather and navigational resources. I have (2) VHF radios but the iPhone is more direct when accessing emergency services other than the Coast Guard. And yes I use the iPhone for work while sailing. It is also a great WiFi hub for other devices. I sail mostly in the San Francisco Bay but even when I go up and down the California coast I still get a signal and it keeps getting stronger with the new iPhones. Seriously, I would not sail without one and I also take my iPad Pro just in case.

Thanks for the added perspective. I share your view that the Apple/TSMC is a game changer; And further that this duo of design and fab leadership plays a pivotal role in the broader digital transformation.

We can only imagine where they will take us with Spatial Computing, mindful that TSMC makes the R1 chip, which may be dubbed the spatial computer; and plays a role in the displays for Vision Pro.

 

[hist78]

Thanks for the added perspective. I share your view that the Apple/TSMC is a game changer; And further that this duo of design and fab leadership plays a pivotal role in the broader digital transformation.

We can only imagine where they will take us with Spatial Computing, mindful that TSMC makes the R1 chip, which may be dubbed the spatial computer; and plays a role in the displays for Vision Pro.

Without Apple's processors to be the guinea pig to shoulder so much risks of a new node, the speed of progress will be slower and the price to adopt a new node can be cost prohibited for everyone.

 

[IanD]

Without Apple's processors to be the guinea pig to shoulder so much risks of a new node, the speed of progress will be slower and the price to adopt a new node can be cost prohibited for everyone.

You could also say that without Apple's demand for a new process half-node every year to coincide with their next product rollout, TSMC would have more freedom to push out processes which coincided with notable improvements in technology than being locked into a fixed yearly timescale... ;-)

But it's undeniable that Apple's needs do give TSMC the confidence that there *will* be a massive customer for a new yearly half-node, which is then available for everyone else shortly afterwards.

I don't think this reduces the cost for everyone, the cost of an N3 tapeout is eye-watering -- but Apple as the first big customer doesn't care, their revenues and margins are so massive that NRE is a mere drop in the ocean for them...

 

[Fred Chen]

90% of 3nm not the proposed N3E seems to imply N3E didn't convince enough yet, or else the actual capacity is simply not there yet.

 

[hist78]

You could also say that without Apple's demand for a new process half-node every year to coincide with their next product rollout, TSMC would have more freedom to push out processes which coincided with notable improvements in technology than being locked into a fixed yearly timescale... ;-)

But it's undeniable that Apple's needs do give TSMC the confidence that there *will* be a massive customer for a new yearly half-node, which is then available for everyone else shortly afterwards.

I don't think this reduces the cost for everyone, the cost of an N3 tapeout is eye-watering -- but Apple as the first big customer doesn't care, their revenues and margins are so massive that NRE is a mere drop in the ocean for them...

"You could also say that without Apple's demand for a new process half-node every year to coincide with their next product rollout, TSMC would have more freedom to push out processes which coincided with notable improvements in technology than being locked into a fixed yearly timescale... ;-)"

I believe Intel does have this type of freedom

 

[IanD]

90% of 3nm not the proposed N3E seems to imply N3E didn't convince enough yet, or else the actual capacity is simply not there yet.

The "earlier report" saying Apple have 90% of 3nm shipments is (was?) true because Apple is the only big customer for N3 and N3E shipments for other customers have not ramped up yet. As soon as this happens Apple's percentage will drop off.

 

[IanD]

"You could also say that without Apple's demand for a new process half-node every year to coincide with their next product rollout, TSMC would have more freedom to push out processes which coincided with notable improvements in technology than being locked into a fixed yearly timescale... ;-)"

I believe Intel does have this type of freedom

Indeed, because unlike Apple they don't have to roll out a new iPhone every year in time for the big Xmas market... ;-)