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Lately, I have been pondering about to find an open gate during dynamic power analysis. Theoretically, it will have high impedance and draws more current. Is it something that we can find out during this analysis? Its just my curiosity to know whether gate level power analysis can find it.
If any of you have used any tools or methods to determine this?
Several FastSPICE provide dynamic e static circuit checks that could cover this issue. The possible issues in a pure dynamic environment will be:
1) reach in a reasonable time the evaluation point
2) apply such a command in a time continuum (I suggest to move to a sampled approach)
3) coverage, in huge design you have no enough CPU time to scroll all possible scenarios (I suggest to use also a static approach) Posted by Alessandro Valerio
Gate level power analysis tools are driven by output (VCD, FSDB, SAIF) of simulations - gate-level or RTL. I don't know of a deterministic way to find an 'open gate' - standard cells libraries are typically not characterized for tri-state (i.e. high impedance) states in the energy tables, but looking for 'unknown' ('X') states or, depending on your simulator setup, also 'Z' states can give you an idea where these gates are in your design. For power consumption calculations, different gate-level power analysis tools apply different heuristics since they have to deal with truly 'unknown' voltage levels in this case. I agree that fast-SPICE simulators have a better set of capabilities in this area, but capacity is more limited.
Let me add few more points to my question, I was meddling with gate level netlist to implement the small block and it so happened I didn't tie the gate to a driver. I had to find that after I complete everything in back end. I do IR analysis but it is not possible to find the undriven nets. Never had a chance to do Dynamic analysis. Logically, if any power analysis tool knows the connectivity and it can trace it back to determine whether it has issues. With lack of experience in Dynamic analysis, I do not know whether it is feasible to find it during the process.
Most tools have pre-simulation checks that will readily find a gate that is genuinely floating. For example, even a pure DC convergence check in spice or fastspice simulators will provide a warning if there is a floating node. Failing that, basic logic checks as described by wruby will be suitable.
In principle DC current analysis could also find the floating gate - if the preliminary internal node-sets can be at mid-rail. DC power analysis is dependent on the same data - so it can only find the same things that you set up in the first instance.
Just shoooting from the hip a little, if a gate path were open, the quite substantial input capacitance of the driven MOSFET would not be seen. There would not be pulses of charging and discharging current flowing. Could that be what you'd want to look for? Posted by John Dunn
True open is one thing. But in analog and mixed signal circuits you sometimes get a weak drive which can lead to significant static current. I use to simulate standby current sweeping the simulator gmin parameter. That reveals most weak drives. Posted by Jean-Francois Debroux
True open is one thing. But in analog and mixed signal circuits you sometimes get a weak drive which can lead to significant static current. I use to simulate standby current sweeping the simulator gmin parameter. That reveals most weak drives. Posted by Jean-Francois Debroux