Samsung strikes chip deal with Apple

[user_2013101]

but I would say it's almost impossible to start with 90% yield in a new node.

The 16FF+ is not exactly a “new node” per se. It is, as I stated before, the final stage of a carefully planned and executed "phrased approach", to overcome the hurdles of FinFET at 14/16nm that still bog down Intel and Samsung.

The 16FF+ is built on the top of the basic 16FF, whose risk production started back in Nov 2013. That is, it took a whole year to reach the plus version’s high "initial" yield. It would be 3 years if counting from the beginning of 20nm.

It’s feasible to begin the volume production with good yields immediately – the ultimate goal of this gradual approach anyway.

TSMC didn’t deliver any miracle; it brilliantly accumulated the accomplishments of prior nodes to render a seemingly sudden success of 16FF+. The fact that 90% of equipments are identical between 20nm and 16nm productions testifies to this programmatic and accumulative approach.

It misses the big picture to claim that Intel’s 14nm leads by a generation because TSMC’s 16nm is 20nm with FinFET, which is merely a stepping stone on the way to 16FF+. Not to mention that 20nm A8 demonstrates higher transistor density than 14nm Core-M.

I expect the 16FF+ to exceed Intel’s 14nm at least in some areas, such as density and application versatility.

 

[Brianhayes]

The 16FF+ is not exactly a “new node” per se. It is, as I stated before, the final stage of a carefully planned and executed "phrased approach", to overcome the hurdles of FinFET at 14/16nm that still bog down Intel and Samsung.

The 16FF+ is built on the top of the basic 16FF, whose risk production started back in Nov 2013. That is, it took a whole year to reach the plus version’s high "initial" yield. It would be 3 years if counting from the beginning of 20nm.

It’s feasible to begin the volume production with good yields immediately – the ultimate goal of this gradual approach anyway.

TSMC didn’t deliver any miracle; it brilliantly accumulated the accomplishments of prior nodes to render a seemingly sudden success of 16FF+. The fact that 90% of equipments are identical between 20nm and 16nm productions testifies to this programmatic and accumulative approach.

It misses the big picture to claim that Intel’s 14nm leads by a generation because TSMC’s 16nm is 20nm with FinFET, which is merely a stepping stone on the way to 16FF+. Not to mention that 20nm A8 demonstrates higher transistor density than 14nm Core-M.

I expect the 16FF+ to exceed Intel’s 14nm at least in some areas, such as density and application versatility.

Interestingly your points are corroborated by William Holt when he said that TSMC would start 16nm production in "early 2015".

 

[lefty]

I wonder if people are just too focused on the the Apple contract. Next year there's going to be more demand for 14/16nm than there is supply. Really Nvidia and AMD were ment to update their GPU products one year ago, but couldn't because Apple had booked up all 20nm capacity and FinFET wasn't ready. Maxwell was origonally never ment to be on 28nm. Nvidia had to change their plan because the delayed nodes. And the rest of the players are the same, all chomping at the bit for FinFET.
So, if TSMC were to get A9 and A9X that would just mean there would be no capacity for Qualcomm, Nvidia, etc. and they would have to use Samsung's 14nm and the situation is reversed if Samsung get the A9 contract.

 

[Arthur Hanson]

TSM has numerous fabs to upgrade and would unload low margin work at older fabs than sacrifice long time good customers. Also TSM engineers have pushed fabs to run well over 100% many times, if you have followed them for long time.

 

[lefty]

TSM has numerous fabs to upgrade and would unload low margin work at older fabs than sacrifice long time good customers. Also TSM engineers have pushed fabs to run well over 100% many times, if you have followed them for long time.

But all that takes time and the customers want it as soon as possible. It took 6 months for TSMC to ramp up 20nm enough to meet Apple's demands.

 

[astilo]

TSM has numerous fabs to upgrade and would unload low margin work at older fabs than sacrifice long time good customers. Also TSM engineers have pushed fabs to run well over 100% many times, if you have followed them for long time.

You simply cannot commit to a customer of yours any number above or even equal to 100%. End of the story.
On top of that, if you can go over 100% so many times, either are you cheating or your capacity models are wrong (at least partially).

 

[Arthur Hanson]

I have seen equipment pushed beyond its stated limits in production processes, labs, in the field and on the race track. Like my professors said, very little is designed with zero margin, even in mission critical items and equipment. I've rarely seen anything that couldn't be pushed 5% at least. It's learning the equipment and processes. No designer I know of can design dead on 100 % capacity. They definitely don't want to fall low and subject themselves to penalties and legal issues or lots of expensive tech time and fixes in the field. If anything they design in some slack and if they can't they test it and set the limits a bit lower. It isn't a matter of right or wrong, but almost no one knowing exactly the precise limit they design for, especially something with as many variables as an entire fab line with many, many processes. When you add up the entire time stack, sometimes the variances can be quite large. In the nuclear faciltiy I worked at, I'm sure some of the tolerances were quite large. I'm sure over time the TSM engineers will find slack they can eliminate, just like they improve the yield.

 

[user_2013101]

I wonder if people are just too focused on the the Apple contract. Next year there's going to be more demand for 14/16nm than there is supply. Really Nvidia and AMD were ment to update their GPU products one year ago, but couldn't because Apple had booked up all 20nm capacity and FinFET wasn't ready. Maxwell was origonally never ment to be on 28nm. Nvidia had to change their plan because the delayed nodes. And the rest of the players are the same, all chomping at the bit for FinFET.
So, if TSMC were to get A9 and A9X that would just mean there would be no capacity for Qualcomm, Nvidia, etc. and they would have to use Samsung's 14nm and the situation is reversed if Samsung get the A9 contract.

I agree that 16nm capacity may be insufficient next year. TSMC did reiterate several times that the 16nm progression has been quicker than 20nm. I believe it is doing its best to pump up capacity without sacrificing yields. But, at this point, it’s unknown how much TSMC can squeeze out.

NVDA’s 20/16nm chips:

Indeed, TSMC gave priority to Apple, and thus NVDA didn’t get 20nm allocation, mainly because Apple is willing to pay premium prices to secure whatever needed. It leads to the record profits and higher gross margins at TSMC.

The less known part of the story: TSMC seems to figure NVDA, unlike Apple, can’t turn to other foundries easily and it’s ok to let it wait. Despite Jen-Hsun Huang and Morris Chang being personal friends, business is business.

Certainly, nobody likes to be taken for granted. As a result, earlier this year, at conference calls, NVDA openly badmouthed the 20nm node, to vent its displeasure. Approaching Samsung’s 14nm process was another gesture from NVDA.

I believe the two companies had since reconciled. NVDA will be given 16nm capacity next year. By the end of 2015, NVDA may deliver some super graphic cards that blow away benchmarks.

 

[astilo]

I have seen equipment pushed beyond its stated limits in production processes, labs, in the field and on the race track. Like my professors said, very little is designed with zero margin, even in mission critical items and equipment. I've rarely seen anything that couldn't be pushed 5% at least. It's learning the equipment and processes. No designer I know of can design dead on 100 % capacity. They definitely don't want to fall low and subject themselves to penalties and legal issues or lots of expensive tech time and fixes in the field. If anything they design in some slack and if they can't they test it and set the limits a bit lower. It isn't a matter of right or wrong, but almost no one knowing exactly the precise limit they design for, especially something with as many variables as an entire fab line with many, many processes. When you add up the entire time stack, sometimes the variances can be quite large. In the nuclear faciltiy I worked at, I'm sure some of the tolerances were quite large. I'm sure over time the TSM engineers will find slack they can eliminate, just like they improve the yield.

Do not get me wrong, I agree. But tolerances are there for a good reason. If you have a capacity model, well, that the maximum amount you can promise/guarantee to a customer (and foundries have many customers to satisfy). Sure, sometimes you can sell products that you have produced in excess, but that's another story.
If I ask you, as a customer of yours, what is the maximum amount of chips you can supply me in a month, well, you must give me a solid number (you pay huge money if you cannot eventually deliver what you have promised).

 

[IanD]

The 16FF+ is not exactly a “new node” per se. It is, as I stated before, the final stage of a carefully planned and executed "phrased approach", to overcome the hurdles of FinFET at 14/16nm that still bog down Intel and Samsung.

The 16FF+ is built on the top of the basic 16FF, whose risk production started back in Nov 2013. That is, it took a whole year to reach the plus version’s high "initial" yield. It would be 3 years if counting from the beginning of 20nm.

It’s feasible to begin the volume production with good yields immediately – the ultimate goal of this gradual approach anyway.

TSMC didn’t deliver any miracle; it brilliantly accumulated the accomplishments of prior nodes to render a seemingly sudden success of 16FF+. The fact that 90% of equipments are identical between 20nm and 16nm productions testifies to this programmatic and accumulative approach.

It misses the big picture to claim that Intel’s 14nm leads by a generation because TSMC’s 16nm is 20nm with FinFET, which is merely a stepping stone on the way to 16FF+. Not to mention that 20nm A8 demonstrates higher transistor density than 14nm Core-M.

I expect the 16FF+ to exceed Intel’s 14nm at least in some areas, such as density and application versatility.

Comparing densities of A8 and Core-M is comparing apples to oranges, one is an ARM mobile core optimised first for power/density (small cheap chip) and second for speed , the other is an x86 laptop/desktop core optimised first for power/speed and second for density.

Saying that 16FF+ will exceed Intel 14nm in density is another apples-to-oranges comparison; 16FF+ is an SoC process with 64nm metal pitch (3 LELE DP metal layers), Intel's is a CPU process with 52nm metal pitch (8 SADP DP metal layers). If you look at the raw numbers Intel's process is a lot more dense (gate and fin pitch is also smaller) but layout for irregular structures will be a lot more difficult because of SADP.

Basically Intel's process is more aggressive, lower yield, higher raw density, much harder to use with little available IP, and more expensive -- which is exactly what they want for their high-margin CPUs. TSMCs is less aggressive, higher yield, lower raw density, easier to use with a lot of available IP, and cheaper -- which is exactly what they want for their SoC customers. Neither is "better" any more than a motorbike is better than a truck, it all depends what you want to do with them.

 

[Arthur Hanson]

But all that takes time and the customers want it as soon as possible. It took 6 months for TSMC to ramp up 20nm enough to
meet Apple's demands.

It does take time, but they can run capacity projects in parallel rather than linear. I have done this personally on projects where time is mission critical. While TSM engineers are still perfecting the process on one fab they can be upgrading other fabs and if done right and with a little luck the time lines will meet with the process being perfected at the same time the additional line is ready to go. TSM managers and engineers and especially Morris Chang have shown strategic use of your resources(people, physical, IP and relationship) can be as important and even more inportant than the resources themselves. I personally feel Morris has stepped down from day to day and is now focused on where his greatest value is and that's the role of the grand master of strategy in the semi industry. He has proved this skill set beyond any shadow of a doubt and this is perhaps his strongest skill among the many skill sets he has mastered. I also have no doubt they have also mastered working with suppliers like AMAT as part of their stratigic plan. Comments and thoughts on this welcome and wanted

 

[astilo]

Saying that 16FF+ will exceed Intel 14nm in density is another apples-to-oranges comparison; 16FF+ is an SoC process with 64nm metal pitch (3 LELE DP metal layers), Intel's is a CPU process with 52nm metal pitch (8 SADP DP metal layers). If you look at the raw numbers Intel's process is a lot more dense (gate and fin pitch is also smaller) but layout for irregular structures will be a lot more difficult because of SADP.

Basically Intel's process is more aggressive, lower yield, higher raw density, much harder to use with little available IP, and more expensive -- which is exactly what they want for their high-margin CPUs. TSMCs is less aggressive, higher yield, lower raw density, easier to use with a lot of available IP, and cheaper -- which is exactly what they want for their SoC customers. Neither is "better" any more than a motorbike is better than a truck, it all depends what you want to do with them.

I fully agree

Comparing densities of A8 and Core-M is comparing apples to oranges, one is an ARM mobile core optimised first for power/density (small cheap chip) and second for speed , the other is an x86 laptop/desktop core optimised first for power/speed and second for density.

Mhm, nope. A8 is definitely not a small chip, and it is cheap, only if compared with the Core M (Intel problem in this case I would say).
Intel Core M: 1.3B xtors, 82mm^2
Apple A8: 2B xtors, 89mm^2
Apple A8X: 3B xtors, 125mm^2

On top of that, A8 is more power efficient than the core M and in terms of performance, already damned close:

View attachment 12676

View attachment 12677

Oh, I forgot, core M costs roughly 6x the A8.

 

[user_2013101]

Comparing densities of A8 and Core-M is comparing apples to oranges, one is an ARM mobile core optimised first for power/density (small cheap chip) and second for speed , the other is an x86 laptop/desktop core optimised first for power/speed and second for density.

Saying that 16FF+ will exceed Intel 14nm in density is another apples-to-oranges comparison; 16FF+ is an SoC process with 64nm metal pitch (3 LELE DP metal layers), Intel's is a CPU process with 52nm metal pitch (8 SADP DP metal layers). If you look at the raw numbers Intel's process is a lot more dense (gate and fin pitch is also smaller) but layout for irregular structures will be a lot more difficult because of SADP.

For a long time, Intel is considered the leader of chip-making technology. Its models have been adopted to gauge the processes.

Intel focuses on transistor shrinkage. Smaller transistors lead to higher density and performce, and lower costs. Therefore, progresses are measured primarily on such scaling.

However, shrinking transistor is not the only way. For example, integration alone, in the absence of transistor scaling, improves overall costs and performances among mobile SoCs. Intel is stilling struggling to accomplish such integration. Its integrated SoC won’t arrive till sometime in 2016.

To make matter worse, many commentators measure transistor size by the dimensions of a few pitches, such as M1 pitch, perhaps due to the Intel bias. As demonstrated by the comparison between A8 and Core-M, the pitch geometry is not a good indicator of the actual density. Other factors, perhaps like Inter-connectors, may be more important. Multiplying M1P by GP further worsens a bad metric to start with.

Intel advantages are falsely concluded if you look at only a few selective measurements of pitches. But, by real density or integration or versatility, Intel is actually in disadvantage.

 

[Arthur Hanson]

Based on the discussion and other information, I have come to the conclusion that when cost, performance, power consumption, time between generations, time to market and outright innovation TSM has taken the lead from Intel. Even the core of Intel's dominance, the Wintel monopoly, is under attack from Nvidia and Qualcom. The next year will show who is actually winning the game. Samsung took themselves out of the game by burning Apple and setting the example that if they are willing to burn the world's biggest corporation, they are willing to burn anybody. Morris Chang came back out of retirement not for money, but for legacy and a sense of duty as TSM is the core of Taiwan's tech industry. He has established himself, along with Steve Jobs and Tim Cook, among a very select group of master strategists of the world's tech industry.

 

[user_2013101]

Indeed, 20nm A8 is denser than 14nm Core-M, by a wide margin.

A8: 2 billion transistors on 89mm2 die = 22.47 millions of transistors per mm2

Core-M: 1.3 billion on 82mm2 = 15.85 millions per mm2

Therefore, A8 packs 41.76% more transistors than Core-M. (22.47 – 15.85) / 15.85 = 41.76%)

A8x is denser than A8: 3 billion on 128mm2 = 23.44 millions per mm2. The comparison is even more lopsided: at 48% denser over Core-M.

(Some reports estimate the A8x die size at 123 or 125 mm2; I use the most conservative one of 128.)

 

[hist78]

Based on the discussion and other information, I have come to the conclusion that when cost, performance, power consumption, time between generations, time to market and outright innovation TSM has taken the lead from Intel. Even the core of Intel's dominance, the Wintel monopoly, is under attack from Nvidia and Qualcom. The next year will show who is actually winning the game. Samsung took themselves out of the game by burning Apple and setting the example that if they are willing to burn the world's biggest corporation, they are willing to burn anybody. Morris Chang came back out of retirement not for money, but for legacy and a sense of duty as TSM is the core of Taiwan's tech industry. He has established himself, along with Steve Jobs and Tim Cook, among a very select group of master strategists of the world's tech industry.

TSMC and Morris Chang will definitely be a case to study not only in semi industry but also in business strategy and leadership.

Stanford Engineering Hero Lecture: Morris Chang in conversation with President John L. Hennessy

https://www.youtube.com/watch?v=wEh3ZgbvBrE

 

[user_2013101]

TSMC’s processes vs. the Intel model

The TSMC methodology is incompatible with the Intel’s development path of nodes and processes, as illustrated by the 20/16nm node(s), which can be viewed as separate nodes or as progressive processes under one big node.

From my observation, this TSMC approach might have been initiated since at least 28nm node, which, over time, has evolved into 5 different processes, with the latest 28HPC launched only several months ago, 3 years after the first mass production of the node. 20/16nm node pushes this strategy further, to the point that processes qualify as separate nodes.

The Intel-style definition of nodes does not quite apply to TSMC.

Another big difference: the older nodes at TSMC never go away; instead, they keep getting upgraded to meet new demands.

For example: Apple’s cutting-edge Touch ID chip (fingerprint sensor/IC) is built from TSMC’s upgraded 180nm node. RF CMOS is done at 90nm. Altera’s MAX 10 FPGAs uses the 55nm embedded flash process. Etc. Etc.

500nm and older processes, which you may think should be in museum exhibitions instead of industrial applications, are alive and well at TSMC, churning out chips and generating revenues.

The older nodes are designated for more expansions, to serve the rising demands from wearable and IoT devices.

Currently TSMC runs well over a hundred productive processes to manufacture over 1,000 different chips, including the Intel 3G/4G modems (XMM 6360/7160/7260) and the Intel’s first integrated mobile SoC SoFIA with Atom cores inside. The TSMC “manufacturing excellence” is not an empty slogan.

The TSMC versatility is quite different from the Intel model of concentration.

The management report of TSMC 3Q14 includes the revenue breakdown by nodes:
Taiwan Semiconductor Manufacturing Company Limited

It is unreasonable for Intel, pretty much a one-part company, to claim superior chip-making technology than TSMC.

P.S.
16FF+ may not be the end of the 20/16nm node. There is rumor that, beyond the plus version, TSMC may add a 16FF Turbo (or by whatever names), which may implement incremental enhancements, or merely special customization for certain clients.

 

[Arthur Hanson]

User, Morris Chang has clearly stated many, many times TSM will take technology from its latest nodes and apply them to its older nodes. Clearly TSM leverages its technology for maximum return as a matter of company strategy.