Samsung reiterates use of EUV in 7nm

[lefty]

There was some speculation that Samsung might change it's plan to use EUV for 7nm, as it's unlikely that EUV will be ready for 2018. However, in Samsung's latest earning call they reiterated their commitment to EUV:

The second question, regarding the System LSI side, is, currently, how much of a yield are you seeing on your 10nm production? And during the previous, last quarter's conference call, you mentioned that you're planning to use EUV technology for the 7nm, but I guess since then the industry trend is to not use EUV for 7nm. I'm wondering if you've changed your strategy as well.
...
Unidentified Company Representative
[Interpreted] We cannot give you the exact internal yield that we're seeing on the 10nm, but I can say that the yield is according to our plan, what we had expected and planned for. And the current plan is to have that commercially adopted on the flagship model next year.
The 7nm, we still plan to use EUV and we're going to maximize the advantage of the EUV technology so that we have improvements in terms of performance, power, as well as scalability, which are the key features of semiconductors.

Samsung Electronics' (SSNLF) Management on Q3 2016 Results - Earnings Call Transcript | Seeking Alpha

 

[Fred Chen]

They didn't say when they plan to use it, at least in the quote above. The truth is, there are still a large number of issue for EUV to solve. It is difficult to imagine anyone daring to use it before Intel 7nm.

 

[lefty]

Samsung said 7nm was planned for late 2018 in a EETimes article:

As part of the news Samsung revealed it will skip the 7nm node with immersion lithography planned by rivals TSMC and Globalfoundries. Instead it aims to have in production a 7nm process with extreme ultraviolet lithography in late 2018, as much as a year before current industry estimates say EUV systems will be ready for volume production.

Samsung to Ship 10nm SoCs in 2016 | EE Times

 

[Fred Chen]

Samsung said 7nm was planned for late 2018 in a EETimes article:

Samsung to Ship 10nm SoCs in 2016 | EE Times

Thanks for the referred article. Again, it would be too early, given EUV's problems. But also, it seems to not make so much difference in terms of benefits. Only a few layers would benefit from mask reduction.

 

[Al Putman]

I suspect that Samsung will have both multi-patterning immersion lithography and EUV versions of their "7nm" node (in that order).

 

[IanD]

It's a strategy issue for "7nm" -- do you push SADP immersion as far as possible (known technology and equipment, lower risk) to get to market faster (and be surer that you'll succeed) but accept more restrictive design rules and lower density, or back the unknown EUV horse to get a denser process with less restrictive rules but probably later to market and certainly with more risk?

Given that nobody has got EUV even close to mass production yet - and this is when new issues always emerge with any new technology -- I also don't think that Samsung will bet the farm on being the first to jump to EUV with no way back if there are any problems, in the same way that TSMC won't have a plan to move 7nm to EUV if it does come up with the goods in time.

 

[lefty]

I assume it's not trivial to redesign a node based on EUV to a node based on immersion and it would delay the rollout considerably. So, supposing EUV is not ready until 2019, that would delay Samsung's 7nm EUV node by a year, or maybe only 9 months, whereas switching the entire node to immersion would take more or less the same time. Therefore, they really gain nothing.

 

[Fred Chen]

Samsung doesn't even have the tools yet.

 

[Fred Chen]

I assume it's not trivial to redesign a node based on EUV to a node based on immersion and it would delay the rollout considerably. So, supposing EUV is not ready until 2019, that would delay Samsung's 7nm EUV node by a year, or maybe only 9 months, whereas switching the entire node to immersion would take more or less the same time. Therefore, they really gain nothing.

Just checked Samsung's 10nm paper at VLSI 2016, they already used SADP in FEOL.