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Samsung 10LPU (3rd generation process) an actual shrink

F

Fred Chen

Moderator
It looks like Samsung's third generation 10nm process (10LPU) is an actual shrink. It should be a heads-up since it could be edging closer to (if not surpass) TSMC 7nm. 10LPE/LPP used triple patterning, 10LPU could see the introduction of SADP.

Samsung Expands its Advanced Foundry Offerings with 14LPU and 10LPU Processes – Samsung Global Newsroom

"Samsung’s third-generation 10nm process, 10LPU, will provide area reduction compared to its previous generations (10LPE and 10LPP). Due to limitations of current lithography technologies, 10LPU is expected to be the most cost-effective cutting-edge process technology in the industry. Together with the second-generation 10nm process (10LPP) that offers an extra performance boost from 10LPE, 10LPU is positioned to meet the needs of an extended range of applications that can benefit from the advanced 10nm process."


 
My guess is this is in direct response to TSMC 7nm. Samsung is a very competitive company and will spare no expense to be the technology leader. I really do think TSMC did a smart thing naming it 7nm versus 10nm+ or something like that. It will be really interesting to see who has EUV in production first. I would not count out Samsung. This truly will be a badge of honor in the foundry business.
 
I would be interested who would use SAQP first in the near future (actually I had thought it would be in use by now). EUV is like an endless marathon.
 
Fred Chen said:
I would be interested who would use SAQP first in the near future (actually I had thought it would be in use by now). EUV is like an endless marathon.
Click to expand...
...which is definitely going to start next year, and has been going to for the last ten years... ;-)
 
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Fred Chen said:
It should be a heads-up since it could be edging closer to (if not surpass) TSMC 7nm.
Click to expand...
The fact that Samsung don't say how much area reduction, indicates to me that it's in fact quite small and it's pretty unlikely that Samsung would call it "10nm" if it was a major shink.
 
lefty said:
The fact that Samsung don't say how much area reduction, indicates to me that it's in fact quite small and it's pretty unlikely that Samsung would call it "10nm" if it was a major shink.
Click to expand...

I'm guessing that it will equal TSMC 10nm. Right now Samsung 10nm is not quite as dense. I'm still hearing that Samsung 10n has yield challenges so they had better fix that first.
 
lefty said:
The fact that Samsung don't say how much area reduction, indicates to me that it's in fact quite small and it's pretty unlikely that Samsung would call it "10nm" if it was a major shink.
Click to expand...

At VLSI Technology 2016, Samsung reported 10nm had metal half-pitch of 24 nm, so I am assuming they shrunk down to around 21 nm (~10% shrink). Previously they had triple patterning for bidirectional metal, so I guess they went to unidirectional SADP like Intel and TSMC. SADP is limited to around 40 nm pitch. Referring to the "limitations of current optical technologies", it implies it reached such a limit. Unless TSMC and Intel both used SAQP to go below 40 nm pitch, I think Samsung effectively caught up. Although neither have said definitively, from what I've got around the web, they haven't yet.
 
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Fred Chen said:
At VLSI Technology 2016, Samsung reported 10nm had metal half-pitch of 24 nm, so I am assuming they shrunk down to around 21 nm (~10% shrink). Previously they had triple patterning for bidirectional metal, so I guess they went to unidirectional SADP like Intel and TSMC. SADP is limited to around 40 nm pitch. Referring to the "limitations of current optical technologies", it implies it reached such a limit. Unless TSMC and Intel both used SAQP to go below 40 nm pitch, I think Samsung effectively caught up. Although neither have said definitively, from what I've got around the web, they haven't yet.
Click to expand...
Correct me if I'm wrong, but I believe you can also increase density by improving design rules, layout tweeking etc., without needing any pitch shrink. For instance, TSMC's 20nm has the same pitches as 16nm, yet 16nm is denser.
 
lefty said:
Correct me if I'm wrong, but I believe you can also increase density by improving design rules, layout tweeking etc., without needing any pitch shrink. For instance, TSMC's 20nm has the same pitches as 16nm, yet 16nm is denser.
Click to expand...

Yes, most likely metal track reduction. Here is my estimate for TSMC. At 16nm, it's 32 nm half-pitch. At 10nm, 2.1x density, then at 7nm, another 1.6x density. So 32 nm/sqrt(2.1*1.6) gives 17-18 nm half pitch, a decent full-node pitch shrink. However, if they "cheat" by going from 9 to 7 tracks, they are within 10% of Samsung's published 10nm pitch.
 
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EUV shot noise already seen in 10nm logic at tip locations

For 10nm logic design rules (22/24 nm hp), shot noise effect was already a visible contribution at tip-to-tip and tip-to-space locations although not reported directly as such:

http://euvlsymposium.lbl.gov/pdf/2014/cbfc0f924fff4f178b0f808a8fac7b41.pdf

Slide 14 shows a resist exposed at about half the dose (due to different sensitivity) for ~1.4x CD to get same local CD uniformity, compared to another, lower sensitivity resist.
 
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