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Join Scientific Analog at DVCon U.S. 2023

AmandaK

AmandaK

Administrator
Staff member
FEBRUARY 14TH, 2023

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XMODEL enables analog simulation in SystemVerilog and it's like ringing an analog bell on top of a digital fortress! Especially at this year's DVCon US, you can join a hands-on tutorial, attend a poster presentation, and meet us in person to learn how to verify your analog circuits in SystemVerilog & UVM. Click below for more information.

Meet XMODEL at DVCon U.S. 2023

Tutorial
March 2, 13:30-17:00 PM
Harnessing the Power of UVM for AMS Verification with XMODEL

Learn more

Paper
February 28, 11:00 AM
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers

Learn more

All product names contained herein are the trademarks of their respective holders.

Link to Press Release
 
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