Intel taping out 18A

[mtuyen]

It's a rumour: https://hothardware.com/news/intel-battlemage-tipped-for-beastly-core-upgrade-and-over-3ghz
yeah, "it was always the plan" because they knew Intel 3 wouldn't be ready in 2024 (at least not in enough capacity). It makes no sense to spend billions on a node and then not use it.

It is most likely Intel will use Intel 3 capacity on higher margins products like Xeon than for consumer GPU like Battlemage where Intel still need to prove itself after a bit of a shaky start from Alchemist. Intel may have capacity issues given ASML only produces a couple of dozens machine per year, it really make sense to give the capacity on higher margin products.

 

[MarcL]

I don't understand why the SIPs (interposers) need to be handled by the big 3-5 foundries. It seems to me that the packaging of the chiplets is an independent function whereby the chiplets come from different foundries. I assume that Skywater is focusing on the interposer and SIPs. Is that how you see it? Are there other smaller foundries or packaging companies focused on this? A 180nm process is even overkill for the interposer. I don't feel comfortable with 100% relying on the major foundries as the supplier of the packages.

In principle, you are correct. But, in practice, all significant 2.5D/3D-IC assemblies are designed by a single company and manufactured by a single foundry. The exception to this is HBM which is a standardized market component. But all the chiplets and the interposer are designed by vertically integrated single-company teams. This will probably change over time, but we're not there yet.

 

[cliff]

Understood and not accepted. I must be missing something. It seems like such an obvious opportunity. I have left messages with LA Semiconductor and will contact @jms_embedded company.

Followup question: Is anybody making an HBM (or any memory with high impedence inputs) with pads on budget pitch (110nm). CML is wasteful.

 

[staf]

Understood and not accepted. I must be missing something. It seems like such an obvious opportunity. I have left messages with LA Semiconductor and will contact @jms_embedded company.

In semiconductors everything is about yield. If you do your own multi-foundry chiplet design and have a yield problem it's your own problem to solve. If you use a foundry provided chiplet solution they see yield problems as a problem for them to solve.

 

[cliff]

In semiconductors everything is about yield. If you do your own multi-foundry chiplet design and have a yield problem it's your own problem to solve. If you use a foundry provided chiplet solution they see yield problems as a problem for them to solve.

Oh, I didn't know that TSMC made HBM chips. So we will go with TSMC's 16nm process for our logic chiplet, their HBM chiplet, and their interposer/packaging, and if the SIP doesn't work, we can return the box of parts and get a full refund. It's like the Amazon model. Nice!

 

[nghanayem]

TSMC doesn’t make HBM because they don’t make DRAM. The only choices are SK-Hynix, Micron, and Samsung. TSMC will package it for you on their 2.5 and 3D packaging technology portfolio, but you need to buy the HBM stack from the DRAM manufacturers. As far as I know you don’t buy loose DRAM dies either. You buy your 4 die stack from say Hynix in a pre assembled package, and then you use that however you want.

 

[Tanj]

You buy your 4 die stack from say Hynix in a pre assembled package, and then you use that however you want.

Correct. I have even talked to vendors about the possibility of putting a custom logic die in place at the bottom of the stack instead of the low-function minimal-cost interface chip that is in the pre-assembled package, with them doing the assembly. Their response was to offer that if I would design the functionality for them, they would then own it and sell it back to me if the upfront costs were covered. Yuck.

The DRAM side of the industry completely lacks the foundry mind-set, which keeps innovation choked far behind what we see on the logic side where innovation is rewarded.

 

[cliff]

Thanks, but I was teasing about HBM being made by TSMC. I My point is that not all the chips are done through TSMC (I suppose it can be done at the Samsung fabs), so I am not really comfortable being dependent on one of the majors doing the packaging. Our system allows us to swap between foundry die quickly, design-wise anyway.

Looking at old silicon foundries for packaging seems interesting to me. Even if an old process is aluminum, that is about 50% more resistive. Not so bad. EM is a lot worse with aluminum, so you just need to be careful there. I assume the complication are TSVs.

Stacking onto a logic chip... nah. I am curious how that ends up working out for AMD.

 

[Tanj]

Stacking onto a logic chip... nah. I am curious how that ends up working out for AMD.

There is always a logic chip at the bottom of an HBM stack. It is just very limited in functionality, built with the cheapest process that can support the throughput. Some more interesting things can be done with that location and the TSVs it can access, even under thermal constraints.

 

[cliff]

Always? Even for 2.5D?

 

[Tanj]

Always? Even for 2.5D?

Yes. The base chip translates from the multiple vertical TSV sets running up the stack into the 2.5D HBM IO interface. The TSVs land on this interface chip, with close impedance matching and some logic dealing with redundancy, then the IOs are at the edge of the base chip.

The only implementations of HBM which I am aware of are modules for 2.5D interconnect. The HBM specs are 2.5D PHY.

 

[cliff]

Yes. The base chip translates from the multiple vertical TSV sets running up the stack into the 2.5D HBM IO interface. The TSVs land on this interface chip, with close impedance matching and some logic dealing with redundancy, then the IOs are at the edge of the stack.

That makes sense. That function is directly related to the HBM. Micron, etc would need to do that.

 

[Tanj]

That makes sense. That function is directly related to the HBM. Micron, etc would need to do that.

Right, but what I was asking for was direct access to the TSVs for some CIM functionality that would transform the TSV traffic to something different over the 2.5D interfaces. None of them disagreed it would be a useful idea, but as I said they wanted to own the function themselves, not leave it as our IP (as a foundry relationship does).

There are multiple ways DRAM could be closely integrated with logic, it is not just HBM. But anyone with such an idea has no foundry relationship to support such ventures.

 

[cliff]

What's your DRAM pad pitch? I can do the logic chip.