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Intel is said to have made a $2B takeover offer for chipmaker SiFive?!?!?

Karl S

Member
I was trying to make a simpler point about computer
instruction set architectures in general. von Neumann
beleived that complicated instruction set architectures
that facitated table look up and indexing algorithms was
superior to simple instruction set architectures inluding
autoatons and neural network type architectures.

Doesn't CISC mean complex instruction set? My understanding
of RISC architecture is small number of simple instructions
with limited addressing modes. My claim is that Neumann
was right and that in some theoretical efficiency sense
independent of semiconductor fab technology, CISC
complexity is better.
 

Karl S

Member
Yes, CISC means Complex Instruction Set Computer. Probably any computer that does anything more than Add, Complement, Load, and Store.
Or maybe means does not do multiply or divide. Of course it is expected to do out of order execution and branch prediction because that complexity has so much curb appeal. Most of the time it can mean anything you want it to.
 

BlueNode

New member
It's a bummer that Intel doesn't do something more innovative. The whole industry is just not innovating, which is disappointing. There's nothing new or noteworthy about RISC-V – it's an extremely dated approach, and it's full of the arbitrary preferences of a handful of academics. It's not a scientific product, not the result of serious testing or simulation studies. I'm not even sure what it means for an instruction set to be "open source" or "free". I guess it could help implementers, but it doesn't help users. In fact, I'm not sure why well-funded teams feel the need to use someone else's instruction set at all. Why does Apple bother with Arm, when they could just create their own ISA optimized for their goals and products?

This all makes me wonder about the status of the Mill CPU and Rex Computing. The former is very innovative, and I expected Intel to either buy them or just move a lot faster with similar ideas. Rex is all about eliminating caches, for reasons I don't fully grok. They just have tiny scratchpad memories per core, and tons of cores. I think Peter Thiel had invested, but I didn't understand the point of it if they're announcing their approach to the world years before producing a product – couldn't Intel just move faster with the same basic ideas? Intel has vastly more engineers and scientists than a tiny startup, so it didn't make sense.

It would be neat if someone took a clean-sheet approach and designed an ISA from a rigorous process of instruction discovery and synthesis. It would start by asking something like "What instructions are most useful given basic assumptions about the tasks of computers and the physical constraints of silicon transistors?" You could reapproach energy use and various tradeoffs from scratch, and would probably discover some interesting opportunities.
 

Karl S

Member
It's a bummer that Intel doesn't do something more innovative. The whole industry is just not innovating, which is disappointing. There's nothing new or noteworthy about RISC-V – it's an extremely dated approach, and it's full of the arbitrary preferences of a handful of academics. It's not a scientific product, not the result of serious testing or simulation studies. I'm not even sure what it means for an instruction set to be "open source" or "free". I guess it could help implementers, but it doesn't help users. In fact, I'm not sure why well-funded teams feel the need to use someone else's instruction set at all. Why does Apple bother with Arm, when they could just create their own ISA optimized for their goals and products?

This all makes me wonder about the status of the Mill CPU and Rex Computing. The former is very innovative, and I expected Intel to either buy them or just move a lot faster with similar ideas. Rex is all about eliminating caches, for reasons I don't fully grok. They just have tiny scratchpad memories per core, and tons of cores. I think Peter Thiel had invested, but I didn't understand the point of it if they're announcing their approach to the world years before producing a product – couldn't Intel just move faster with the same basic ideas? Intel has vastly more engineers and scientists than a tiny startup, so it didn't make sense.

It would be neat if someone took a clean-sheet approach and designed an ISA from a rigorous process of instruction discovery and synthesis. It would start by asking something like "What instructions are most useful given basic assumptions about the tasks of computers and the physical constraints of silicon transistors?" You could reapproach energy use and various tradeoffs from scratch, and would probably discover some interesting opportunities.
Why does Apple bother with Arm, when they could just create their own ISA optimized for their goals and products? Isn't that what Apple's M1 chip is?

"It's a bummer that Intel doesn't do something more innovative". They don't want to kill the X86 goose that is laying all those golden eggs.

" They just have tiny scratchpad memories per core, and tons of cores". I think those cores probably do specific tasks, so instead of the typical fetching a line/block of data from memory just on the idea that the program maybe doing a matrix inversion so it may use more than one word in the block.

I am trying to show that today's compilers don't use or give a hoot what the ISA is. They emit an intermediate language and either interpret or JIT compile to the ISA.

I think the next step is to "fergit aboud" the stinking ISA. Use the compiler API, SyntaxWalker and a stack to evaluate expressions. And yes, you can then use a tiny core and embedded memory blocks all running in parallel.

What is really nice is that today's FPGAs can be used to avoid the cost of ASIC development. It only takes a few hundred LUTs and 3 memory blocks out of thousands that are available.
 
Here are some examples from my application Verilog x86_64
flow graph compiler. There is a reason all the fast Verilogs (the evaluation
under SV) run on X86 Linux. Quality of flow graph intermediate form
(there are lots of them) to machine code translation makes the
difference between a slow simulator and a fast one. We tried
stack evaluation but it was at least 20 times slower than current
optimized flow graph machine instruction expansion. Stack
evaluation is why Icarus Verilog is so slow.

I have always wondered why there are not open cores
for the old DEC alpha instruction set. It was great for
flow graph optimization because it allowed smart
compilers some ability to schedule resources. Also,
it was scientifically designed including many very
complicated instructions.
 

Karl S

Member
Here are some examples from my application Verilog x86_64
flow graph compiler. There is a reason all the fast Verilogs (the evaluation
under SV) run on X86 Linux. Quality of flow graph intermediate form
(there are lots of them) to machine code translation makes the
difference between a slow simulator and a fast one. We tried
stack evaluation but it was at least 20 times slower than current
optimized flow graph machine instruction expansion. Stack
evaluation is why Icarus Verilog is so slow.

I have always wondered why there are not open cores
for the old DEC alpha instruction set. It was great for
flow graph optimization because it allowed smart
compilers some ability to schedule resources. Also,
it was scientifically designed including many very
complicated instructions.
Compilers are focused procedural languages, not on Verilog(which is a kind of dataflow language at best). Verilog did not appeal to designers, but because Verilog could be simulated it appealed to management and Verilog was forced on designers. A major problem has always been that the "tool chains" are focused on synthesis, which should come after design/debug. No, there are no decent design/debug tools, except for possibly my BooleToole project that is in process.

Today's compilers use Abstract Syntax Trees and Expression Trees which evolved from Dijkstra's shunting yard algorithm which used a stack to manage operator precedence. How does Verilog handle operator precedence? How does your compiler handle operator precedence?

The Roslyn compiler API issues operands in the sequence for stack based evaluation as well as MSIL which is used for JIT and both work very well. I have no idea what you did or why it was so slow.

MicroSoft project Catapult was based on using FPGAs to evaluate algorithms faster than a CPU running at 10 times the clock speed. My CEngine FPGA is a similar design. Yes, there is a stack inside.
 
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