How real is for GF, UMC, and other 2nd tier foundries to field a common sub-40nm platform?
- Thread starter Paul2
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I see the biggest problem of 2nd tier foundries, is that they are all chasing after a diminishing number of top fabless semis who can pull $10m+ tapeouts, but a giant number of commodity IC, and 3rd tier SoC makers still remain left behind the 40nm wall.
The only player on the market which can claim to have "a real ecosystem" for sub-40nm is TSMC with its OIP, and its own proprietary process. The rest can't claim to have even 1/10th the reusable physical IP, EDA support, backend services, and etc of TSMC for sub-40.
The few outsourcing shops who work on sub-40 projects, will only sign on a post-paid project if the tapeout is at TSMC as well.
The only player on the market which can claim to have "a real ecosystem" for sub-40nm is TSMC with its OIP, and its own proprietary process. The rest can't claim to have even 1/10th the reusable physical IP, EDA support, backend services, and etc of TSMC for sub-40.
The few outsourcing shops who work on sub-40 projects, will only sign on a post-paid project if the tapeout is at TSMC as well.
It has already been attempted, and unfortunately it failed miserably. The IBM common platform alliance foundries all dropped out of the moore's law race except for Samsung. UMC eventually wheezed out their "14nm" process , and GF modified their 7LP BEOL to IBM's 14HP to make their first node since the basket case that was 28nm SOI.
Unless I am misunderstanding what you mean by a common platform. If you mean something like Cliff is talking about isn't that just UCIE?
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Oh, you meant an IP/EDA platform. I don't think that would be possible without having identical DRs and PDKs. But I will refrain from saying much more as I would be speaking WAY out of my depth.
Unless I am misunderstanding what you mean by a common platform. If you mean something like Cliff is talking about isn't that just UCIE?
Why only these guys? If it must be fabed in the US, why not Samsung or TSMC? Especially if you are buying GF14/12LPP, I have to assume Samsung 14/11LPP is even cheaper for the same node. I think TI also does interposers with TI and 3rd party dies, so why not them?
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Oh, you meant an IP/EDA platform. I don't think that would be possible without having identical DRs and PDKs. But I will refrain from saying much more as I would be speaking WAY out of my depth.
Mr. Paul, from what you can see, I agree with you. Perhaps there are solutions that you will soon see.
As far as IP standardization, with foundry technology (and automation) changing so fast, does standardization make sense? Perhaps make first order spec (don't spend 2 years and 900 pages on the spec), then adjust it to customer needs. I expect Mr. Blue to beat me up on this one.
As far as TSMC, I think the whole world is their partner. Everybody makes "IP" for TSMC. They run shuttles ;-)
TI and Samsung have their own ecosystem, no?
As far as IP standardization, with foundry technology (and automation) changing so fast, does standardization make sense? Perhaps make first order spec (don't spend 2 years and 900 pages on the spec), then adjust it to customer needs. I expect Mr. Blue to beat me up on this one.
As far as TSMC, I think the whole world is their partner. Everybody makes "IP" for TSMC. They run shuttles ;-)
TI and Samsung have their own ecosystem, no?
Yes, I meant another IBM style common platform alliance, probably a bit less strict on physical standardisation this time.
Yes, definitely, as a giant amount of companies can't tapeout even on a 10 years old process.
The number of fabless who ever made FinFET ICs is a small fraction of all fabless semis.
Mr. Ng, you read me correctly (as always). I am talking about SIP solutions. They don't really need to be tied together, but together, with an EDA vendor who has automated their layouts (GF14, SKY90), created stdcells, and provide PLLs, Serdes, Pclamps, Bandgaps, etc free with their EDA tools, is it possible that customers could have the ability to MPW out for $2M instead of $10M?
Wouldn't that prevent IP from being compatible and designs from being easily portable. I also think you misunderstand what was common. The component's research R&D was shared, and the general features were similar. But the actual implementation was different from firm to firm. For example AMD/GF, Renesaus, and I think Fujitsu went the SOI route. Meanwhile Samsung and UMC went bulk (don't know what charted did). However on more major things, all of them went together (think gate first HKMG, 14nm being finFET, ect). Another example of the differences is on "7nm" GF went optical while Samsung went heavy on EUV and a bit less dense than GF.
Yes. But from what I hear Samsung unsurprisingly has a smaller ecosystem than TSMC. TI isn't really a contract foundry, but they do collaborate with external companies for making custom systems for the DoD and other private customers.
Beats me I don't know how much money a mask set costs on GF and SKW for the technologies you are interested in.
IBM's alliance died down because they lost in the race to get HKMG, and FinFET to TSMC, and the financial expectations from that were no longer as expected after big clients went to TSM, thus companies bailed out one after another, no longer seeing the reason to pay for the cost of the alliance.
As of now, sub-40 IP is not compatible at all.
SOI, and bulk fabs will of course continue on their current fundamental processes, and nobody will rebuild their fabs, or build new legacy process fabs just to accommodate another alliance. The task is is to market their existing fab capability in a more attractive way for people stuck at 40nm.
If SOI and bulk divide is completely irreconcilable, at least then either SOI, or bulk camp can try to "platformize" on its own
As of now, sub-40 IP is not compatible at all.
SOI, and bulk fabs will of course continue on their current fundamental processes, and nobody will rebuild their fabs, or build new legacy process fabs just to accommodate another alliance. The task is is to market their existing fab capability in a more attractive way for people stuck at 40nm.
If SOI and bulk divide is completely irreconcilable, at least then either SOI, or bulk camp can try to "platformize" on its own
Samsung beat TSMC to HVM on finFETs. I also think that even if AMD stayed on GF, I don't think GF would have had the volume to justify staying in the race. Otherwise I agree, the HKMG debacle was a fatal blow to everyone but Samsung, and everyone except Samsung being late to finFET sealed the deal.
To my knowledge nobody really paid for the alliance, so much as it was joint R&D.
How would you make drop in compatible IP work on nodes that are so different? Doubly so if you made it even less restrictive than the old alliance?
It's a travesty it didn't work though. It would have been so cool having TSMC, Intel, and the whole common platform alliance on the leading edge and with everyone having significant MSS. I guess that would have been too cool to happen in our timeline though
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By theory, everything's possible. But there will be someone winning and someone losing. Since every 2nd tier foundry has different transistors, their customers are all accustomed to their foundries. If somehow foundries form some sort of alliance, then some fabless will be crying out loud, if a new foundry alliance's offering results in a massive change of their own IP portfolio.
Same goes for a foundry. If the alliance wants your foundry to sacrifice by changing new transistors to somewhat far from your technology(but closer to theirs), then you'll not like it.
This is a part of the reason why TSMC's so strong. In order to make Alliance foundry to work, then their offering must be extremely useful(low power, high performance...etc) to make fabless to align to new foundry offerings(good enough to allow them to modify their IPs a lot). But, can they?
Same goes for a foundry. If the alliance wants your foundry to sacrifice by changing new transistors to somewhat far from your technology(but closer to theirs), then you'll not like it.
This is a part of the reason why TSMC's so strong. In order to make Alliance foundry to work, then their offering must be extremely useful(low power, high performance...etc) to make fabless to align to new foundry offerings(good enough to allow them to modify their IPs a lot). But, can they?
Be specific. Who in the company is saying that? Break this down.
Digital designers... doesn't matter. They are process independent, as long as they have plenty of layers to work with (hear that IFS?)
Analog front-end designers (like me). We use the same testbenches to check output impedences, gains, etc and understand the FETs. We also call the foundry and as them the leakage data (I don't trust the spice models on leakage). We migrate and optimize (or change the topology and implement what we should have done in the first place). No big deal, assuming the designs were properly shrink wrapped with their TBs. Note, that is typically the problem. Crappy management allowing for irresponsible behavior. The circuit designers protecting their domains. Better move quickly before the circuit designer leaves and takes all the knowledge with him.
Layout. OK, this is the problem. Automation solves this. It is coming at a design house near you. Layout designers need to find other occupations. Scratch that. Not many exist anymore. Junior level engineers have taken that are over, which is a good thing. They can run EM, RCx, refactor schematic topologies based on layout (bit slicing, etc).
Things are changing too rapidly. Forget standardization. By the time the project is complete, the designs are obsolete. Automation is coming.
hist78
Well-known member
TSMC has 16nm fabs in Taiwan ROC and Nanjing China and another one coming in 2024 in Kikuyo, Kumamoto Japan. To build a fourth one in Arizona might reduce existing fab utilization and politically problematic. TSMC doesn't want to give people an impression that they are trying to kill Intel Foundry Services.
It's impossible to make anything drop-in compatible now without making processes, and design rules mirror copies of each other, and retooling fabs to accommodate that. Of course nobody will be retooling a 10 years old fab just to field some alliance node.
But how real is trying to find some greatest common divisor for major process classes without physically changing the process?
The second route is have a common licenseable sub-40 node for which new facilities will be built. The question is who will be licensing that node, and for how much? GF has a relatively relatively new, and competitive SOI nodes, but why would they license them out?