GlobalFoundries downgraded by Citi amid competition - downturn concerns

[nghanayem]

Mr. Blue: Of course FPGAs are popular and needed, but so are ASICs.

Mr. Ng: Who is knocking 6nm? But why does every foundry need to be leading edge? If you aren't number 1, then you pack up and close? There are lots of customers that don't have $50M NRE budgets. Why is NXP, etc making chips on 16nm?

I never said that. But you can never grow the market if you don’t move along the cost curve. At best you stay a similar size. There’s a reason why there are no more 6 and 4 inch wafer fabs, and 8in seems like it is on the way out if you aren’t getting big fund money from the PRC. Heck it seems like alot of 300mm nodes might be going away. It feels like TSMC and UMC are winding down pre 28nm and moving those customers onto 28. It also seems like the 28 folks are moving to first gen finFETs. And it is well documented that TSMC is trying to move the 16FF holdouts to N7. Even UMC is moving to a 12nm now (how that compares to GF14/12 ofc remains to be seen). My larger point is that eventually GF needs to move onto new nodes, but given their current market position it needs to be done in a cost conscious manner. MRAM and advanced packaging will not be a cure all as they are offered by all of GF’s competitors.

The only technological differentiator I see for GF is that they seem to be pushing for an FDSOI ecosystem in a way their co-development partners haven’t, and that this might be a shield against all of the new players and customers moving to more advanced nodes.

My point is that there is nothing wrong with 16-12nm processes. I believe GF's plan is a good practical plan and should stick with it. They should NOT be allowed to merge with Samsung, Intel, etc. No way.

I don’t have a problem with that node. But we won’t be using it in forever. It is just not cost competitive. Even if a 16/14 ASIC beats an N7 Xilinx chip today, will it beat a Xilinx chip with an A14 array? I’m not convinced it will.

 

[cliff]

Isn't GlobalFoundries more focused now on its 22FDX SOI and 12nm FinFET?

Sorry for the confusion. I call it 14nm because that is the drawn poly size. We should probably call it by the gate pitch and M2 pitch, but just use the old standard (poly pitch). I also call tsmc 12ffc "16nm"

But you can never grow the market if...

GF doesn't have to. The ecosystem around it will.

Advanced packaging (Amkor, etc) allows 16-12nm die to become chiplets.
Layout automation allows the NRE of creating 16-12 simple (want a demo?)
Exotic memory R&D companies allows embedded RAM to become denser.

Even if a 16/14 ASIC beats an N7 Xilinx chip today, will it beat a Xilinx chip with an A14 array?

Yes it will. A custom ASIC on older processes will ALWAYS win (if you have the budget and time). Take a look at a LUT and the switches to get to them. It is disgusting

FPGA are great for prototyping, low/reasonable volume, low NRE, and electronics that plug into a wall, run slow, and have non conductive oil pumped around them

Disclaimer: I put a few guys onto making an eFPGA (embedded into the ASIC). If there are any entrepreneurs out there (@KevinK ) who wants to handle that, please contact me.

 

[nghanayem]

Sorry for the confusion. I call it 14nm because that is the drawn poly size. We should probably call it by the gate pitch and M2 pitch, but just use the old standard (poly pitch). I also call tsmc 12ffc "16nm"

The old standard was never poly pitch. It was gate length. Also why say that 16FF has a poly width (gate length) of 16nm? The width is to quote wikichip 37nm which sounds about right given where the gate lengths on 5"nm" class nodes are.

GF doesn't have to. The ecosystem around it will.

Advanced packaging (Amkor, etc) allows 16-12nm die to become chiplets.
Layout automation allows the NRE of creating 16-12 simple (want a demo?)
Exotic memory R&D companies allows embedded RAM to become denser.

For one this isn't specific to GF or their 14LPP. For two all of that work is just to not lose business. The reason you see ULL, HV, exotic memory,TSV, RF, MEMS, etc is because as mobile and HPC move off a node the foundry needs something to justify why people shouldn't move all products to the cheaper new nodes. This creates a kind of second cost curve for *insert technology here* with customers moving to the newest node that offers their feature Some day soon there will be N5 RF, and the N6RF guys will move to that. In turn they will have N6E to court the N12E folks, and N12 MRAM/N12 BCD to court the 28/22nm folks. On the flip side; GF will eventually run out of new nodes to update with these features and be left behind if they don't eventually move along the curve.

For your applications the current sweet spot for yield, PnP, aerial cost, NRE cost, and features is 16FF/14LPP. Was that the case 5 years ago? My guess (correct me if I am wrong) is that you were doing 28/40nm back then. What happens in 5-10 years in the future when other ASIC makers are on 3.3x the density wafers that cost like 4k a pop and use half the energy? Will your customers buy disag GF14LPP ASICs with MRAM, or buy N7 disag ASICs with MRAM? Heck with cost per FET being so low maybe they can cut out the extra cost and complexity of disag and just do a monolithic design. 10 years ago intel 22nm was in production and intel was struggling with 14nm, meanwhile the foundries were trying to get their first gen finFETs ready for ramp. 10 years in the future, who's to say that EUV mask writing won't get pretty reasonable in cost and that the lower layer count for N5 makes it more cost effective than N7 for folks who are running low volumes (assuming it has feature set parity)? Or maybe OPC/EPE gets to the point that we can do N6 or a relaxed N5 with DUV SALELE? The semiconductor industry is a moving target, you innovate or you die, there is no alternative. One only needs to look at the long trail of the broken bodies of former fab operators to see what I mean.

Yes it will. A custom ASIC on older processes will ALWAYS win (if you have the budget and time). Take a look at a LUT and the switches to get to them. It is disgusting

FPGA are great for prototyping, low/reasonable volume, low NRE, and electronics that plug into a wall, run slow, and have non conductive oil pumped around them

Disclaimer: I put a few guys onto making an eFPGA (embedded into the ASIC). If there are any entrepreneurs out there (@KevinK ) who wants to handle that, please contact me.

Did some quick and probably incorrect math, and I yield to you on this. I didn't realize how few logic gates there were on even modern FPGAs. Back to the topic, will a 14LPP specialty purpose ASIC be able to stand head to head with an A14 general purpose xPU?

 

[cliff]

poly length... sorry. typo.

In my opinion (and other mixed signal circuit designers who I collaborate with), NRE, timelines, and access to a TRUSTED foundry is everything. Saving pennies on area doesn't matter. The goal is to get as much as you can onto silicon (not on the PC board)

Sqeezing the size down for massive amount of SRAM is nice. Squeezing down for a the FPGAs is nice. Getting out to silicon at 2x the area quickly is terrific.

FinFets of ANY size is terrific. 28nm leakages (last I simulated) were horrendous. We use switched capacitors, dynamic logic, etc.

"You innovate you die", sure, but it is likely that customers (including us) will innovate by changing architectures. From what insiders from your company (the design side), Intel designer rely in incremental changes to their designs. That doesn't sound like engineering to me. I bet 16-12nm will still be the sweet spot for all products that don't get plugged into a wall... even 5 years from now. Taxpayers cannot continue to pay for these exponentially rising costs of fighting physics.

Edit: I looked back at what I wrote. I wrote "I call it 14nm because that is the drawn poly size." I didn't write poly pitch. My opinion was that poly PITCH (and M2 pitch) would be a better way of describing the process.

 

[nghanayem]

poly length... sorry. typo.

Sounds like a weird thing to measure a transistor by with how variable that statistic is even within the same design, but if that works for you I won’t judge.

In my opinion (and other mixed signal circuit designers who I collaborate with), NRE, timelines, and access to a TRUSTED foundry is everything. Saving pennies on area doesn't matter. The goal is to get as much as you can onto silicon.

Sqeezing the size down for massive amount of SRAM is nice. Squeezing down for a the FPGAs is nice. Getting out to silicon at 2x the area quickly is terrific.

As automation improves and the IP portfolio grows to reduce design complexity, isn’t there any reason why you won’t eventually be able to design on double patterned N7? You could fit in more functionality within the same bom cost while also offering half the power consumption. Once everything comes together that seems like a no brainer choice for your customers.

“You innovate you die", sure, but it is likely that customers (including us) will innovate by changing architectures.

I was speaking from the fab side. But even with design what happens if a competitor also innovates on arch and uses a more advanced node? Your chip would need to be significantly better architected just to keep up.

From what insiders from your company (the design side), Intel designer rely in incremental changes to their designs. That doesn't sound like engineering to me. I bet 16-12nm will still be the sweet spot for all products that don't get plugged into a wall... even 5 years from now.

Less than a decade ago folks said the same thing about 28nm Cliff. That “this was the end” “finFETs are too expensive” “only premium CPUs could afford to move”. And yet here you are on first gen finFETs with a good cost structure. I would be a fool to bet that the same thing won’t happen for at least N7. Maybe N5 and EUV will finally be that last straw that breaks the camel’s back. A wall that some types of chips will never cross due to the cost of an EUV mask. But in 10 years the semiconductor industry will be doing things I can’t even begin to imagine, so I would never disqualify the possibility that one day your firm will be making tools and IP for chips on some variant of N5.

What I do think will for sure be the case is that the flattening of the cost scaling will definitely slow the rate of transitions from what they used to be. Presumably earlier in your career customers would switch to newer nodes for their ASICs faster than it took you or some of the analog guys on this forum to adopt finFETs. Regardless, I have no reason to believe that this wouldn’t be the trend and that N7 will eventually come (even if it takes a while).

Taxpayers cannot continue to pay for these exponentially rising costs of fighting physics.

I guess design costs have been going out of control, but I can’t really say much one way or the other as I would be far removed from any area of my knowledge. I suppose all of the off the shelf IPs and increasing automation are the solutions needed for your type of chips to move beyond 14LPP.

As for taxpayers they don’t pay for anyone to move along the cost curve. The large fabless firms do that, and they need the economic and P-P benefits to field competitive products. Once they move on to the next shiny thing, the foundries and EDA folks will do what they need to do to remaster the old nodes. They will make the cost and feature set irresistible for all those trailing customers to move onto the next new-old node along the cost curve of their specialty technologies of choice.

 

[cliff]

Sounds like a weird thing to measure a transistor by with how variable that statistic is even within the same design, but if that works for you I won’t judge.

Based on the LV stdcells, but I can start saying 12nm if it reduces controversy

As automation improves and the IP portfolio grows to reduce design complexity, isn’t there any reason why you won’t eventually be able to design on double patterned N7? You could fit in more functionality within the same bom cost while also offering half the power consumption. Once everything comes together that seems like a no brainer choice for your customers.

It takes a lot of work (as you know) to create the correct pitch to use for our layout automation, standard cells, and our policy to have as close to automatic process migration as possible. For example, our 180nm, 40nm, 16nm, and 14nm is almost push button (gf22... not so much), but we need to run the optimizer on all of our DUTs (they always have TBs with them) to tweak them into spec, unless the calibration range is acceptable. We do throw away a little bit of area between tsmc16 and gf14 (oops.... 12 and 12), and the user can squeeze it down with a few minutes of labor per block, and a bit more as you go up in levels of the hierarchy.

7nm... Are you asking about TSMC-DUV or TSMC-EUV. I haven't looked at the rules because I don't have $50M in my bank account. Are the yields better now? The Asianometry guy (and others) scared me.

I was speaking from the fab side. But even with design what happens if a competitor also innovates on arch and uses a more advanced node? Your chip would need to be significantly better architected just to keep up.

Our schtick is TTM, NRE costs, and security. We have the complete suite of EDA tools (more automated than Cadence), pretty darn good analog IP, and lots of circuit designers who can pass security clearances.

Less than a decade ago folks said the same thing about 28nm Cliff. That “this was the end” “finFETs are too expensive” “only premium CPUs could afford to move”.

That is exactly what I told all of my shareholders in September of 2016!

Then a customer asked us to automate FinFETs in October, and I said YES!!!

Hopefully I will be proven wrong again this year. To be quite honest, I thought 90nm was insane.

And yet here you are on first gen finFETs with a good cost structure. I would be a fool to bet that the same thing won’t happen for at least N7. Maybe N5 and EUV will finally be that last straw that breaks the camel’s back. A wall that some types of chips will never cross due to the cost of an EUV mask. But in 10 years the semiconductor industry will be doing things I can’t even begin to imagine, so I would never disqualify the possibility that one day your firm will be making tools and IP for chips on some variant of N5.

What I do think will for sure be the case is that the flattening of the cost scaling will definitely slow the rate of transitions from what they used to be. Presumably earlier in your career customers would switch to newer nodes for their ASICs faster than it took you or some of the analog guys on this forum to adopt finFETs. Regardless, I have no reason to believe that this wouldn’t be the trend and that N7 will eventually come (even if it takes a while).

I guess design costs have been going out of control, but I can’t really say much one way or the other as I would be far removed from any area of my knowledge. I suppose all of the off the shelf IPs and increasing automation are the solutions needed for your type of chips to move beyond 14LPP.

As for taxpayers they don’t pay for anyone to move along the cost curve. The large fabless firms do that, and they need the economic and P-P benefits to field competitive products. Once they move on to the next shiny thing, the foundries and EDA folks will do what they need to do to remaster the old nodes. They will make the cost and feature set irresistible for all those trailing customers to move onto the next new-old node along the cost curve of their specialty technologies of choice.

If you optimists at your win at all costs attitude want to keep pushing the envelope, I will gladly follow.... 5 years behind with my knuckles dragging.

 

[Daniel Nenni]

Isn't GlobalFoundries more focused now on its 22FDX SOI and 12nm FinFET?

Intel and UMC will also be competing in the 12nm foundry business soon. It will be very crowded. More 28nm is coming online. How is GF going to grow revenue?

 

[nghanayem]

Based on the LV stdcells, but I can start saying 12nm if it reduces controversy

I don't really care, I just don't think I have ever seen it is all. When people measure in that direction they usually talk about cell height.

It takes a lot of work (as you know) to create the correct pitch to use for our layout automation, standard cells, and our policy to have as close to automatic process migration as possible. For example, our 180nm, 40nm, 16nm, and 14nm is almost push button (gf22... not so much), but we need to run the optimizer on all of our DUTs (they always have TBs with them) to tweak them into spec, unless the calibration range is acceptable. We do throw away a little bit of area between tsmc16 and gf14 (oops.... 12 and 12), and the user can squeeze it down with a few minutes of labor per block, and a bit more as you go up in levels of the hierarchy.

7nm... Are you asking about TSMC-DUV or TSMC-EUV. I haven't looked at the rules because I don't have $50M in my bank account. Are the yields better now? The Asianometry guy (and others) scared me.

N7 is all optical N6 has a tiny bit of EUV to reduce wafer costs (mostly used for the contacts if memory serves). Yields are very clearly excellent given the titanic die sizes folks spit out. It has also just been a long period of time since first HVM. Doing a reticle buster is something that really is just impossible unless the defect density trend is very healthy. As for Asianometery I do enjoy his content (especially his more historical pieces) and it is mostly pretty accurate (to my knowledge anyways). But not everything is always 100% correct or up to date (once again based on my understanding as a young grasshopper). He doesn't claim to be a savant though, so I don't get uppity about it. Multipatterning is hard, but it is something basically everyone has a lot of expertise in at this point. Same thing with EUV. The difficulty is not doing what has already been done, but going to that next level. As an example take LE^x multipatterning:

Double was hard to do at first, but it is a piece of cake now (part of the reason why TSMC could move from 16FF to 10FF to N7 so fast). Triple and quad gets exponentially worse, but once it's solved; it's solved. Although with that said I don't know if Samsung ever had to go with LE^4. I think 8LPP only needed LE^3, and that 7LPP used EUV so early explicitly so they didn't have to deal with that mess. To my knowledge quad patterning has only ever happened with SAPQ since it is simpler than LE^4 and allows for looser EPE requirements. But Fred would know better if any of the planar NAND nodes ever went with LE^4 instead of SAPQ.

A favorite maxim of mine is "if we can figure out how to make one wafer then we can figure out how to make a million wafers.".

Our schtick is TTM, NRE costs, and security. We have the complete suite of EDA tools (more automated than Cadence), pretty darn good analog IP, and lots of circuit designers who can pass security clearances.

That is why I was unsure if folks like you will ever be able to make the transition to N5 family. But I wouldn't be shocked if over time the cost of an EUV mask went down enough for N5 (and it's lower overall mask count) to be viable for someone with lower volumes such as you and your customers. N7 and maybe N6 should be comparatively smaller mountains to scale. Not a mountain that needs scaling today mind you. But I mountain that I suspect you will eventually need to climb.

That is exactly what I told all of my shareholders in September of 2016!

Then a customer asked us to automate FinFETs in October, and I said YES!!!

Hopefully I will be proven wrong again this year. To be quite honest, I thought 90nm was insane.



If you optimists at your win at all costs attitude want to keep pushing the envelope, I will gladly follow.... 5 years behind with my knuckles dragging.

Nothing wrong with that! You get to enjoy the foundry spreading some of the wealth that their fully depreciated equipment gives them, excellent defect densities, and a far larger list of device types.

Intel and UMC will also be competing in the 12nm foundry business soon. It will be very crowded. More 28nm is coming online. How is GF going to grow revenue?

My guess is that eventually they will have to finish their 7LPP development. It will be kind of expensive to revive it, but far cheaper than starting from scratch. I guess it also depends on what UMC/intel 12nm is. If it is just an extension to UMC 14, then I suppose that GF doesn't really have much to fear given it isn't really changing the landscape beyond creating a larger already depreciated US fab that will be cost and supply chain resiliency competitive with Malta.