simguru
Member
Could you elaborate on the statement above? Why doesn't conventional STA cope with Power Management Techniques?
Thanks,
Christos.
Having sat through a presentation on low-power techniques at Mentor a while back, where it appeared that the approach to verifying the logic that was using variable supply voltages was to keep reloading different sets of SDF data. I'm assuming that most of the current tools were not designed for this use scenario and it's all a big hack.
Power management is largely an analog/mixed-signal problem, and hardly any of the EDA vendors turn up at Accellera looking for support in Verilog-AMS and definitely not in SV at the IEEE. I've had standing proposals for back-annotation and power supply hook-up for years that nobody has shown any interest in. So as far as I can tell most folks are probably just crossing their fingers until they get to the point of layout extraction and fast spice.
I could be wrong, but I would point to Wally Rhines numbers of only 30% of chips working on first pass as an indication that if the parts of the flow I know well are dysfunctional, then it's likely to be pervasive.