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Best Low Power techniques around !!!


New member
Kindly share your thoughts on current low power techniques being employed in industries.
Appreciate if you can share some pros/cons of the same.

Look forward to some response.

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low-power techniques

Here are a few techniques:
  • Clock gating
  • Multiple Vt devices
  • Back/forward biasing of devices
  • Power gating for shutdown
  • State retention
  • Multi-voltage supplies
  • Dynamic voltage scaling
  • Dynamic frequency scaling (Dynamic Voltage and Frequency Scaling - DVFS)
Many of the EDA companies have low power flows, like at Synopsys they have the Lower Power Methodology Manual (LPMM) as a PDF download.
I just blogged about an Apache piece on the top 5 reasons they found that SoC designers were wasting power. The reasons were:

Not using power gating (really important since it improves leakage power as well as dynamic)

Not being aggressive about clock gating and only doing the simplest recirculating mux stuff

Inefficient high-level design architecture

Inefficient implementation

and the biggest reason, missed global clock gating opportunities (turning blocks off when they are not being used, but when they need to be turned back on fast, since otherwise power gating may be even better)
a bit elaboration and classification


Hope this will help you.



Yes, that is a very insightful topic.
IN coursework, we studied using lower voltages, lower leakage technologies etc. But it will be very useful to know how exactly these are implemented in the industry.
Posted by Deepika
A lot can be done a the very high architectural level, even above the chip if you are in control of it. For example, when the US switched from analog to digital cell-phones, the initial implementation kept the analog paging channel where phones are told about incoming calls (since it was shared between old and new standard phones), and just used digital on the voice transfer channels (this was pre-data). So those phones couldn't ever sleep and save power. GSM (and the later IS-136 in the US that did have a digital paging channel) could spend most of their time sleeping since the protocol mean that an incoming call would come on a known time slot every few seconds (nobody noticed their calls being delayed by 4 seconds) and the rest of the time the phone would be powered down. Of course, designers needed to use the techniques already described to actually do this, but changing the paging channel is the big thing that made standby times suddenly a few days.
How about asynchronous logic?

The problem with a lot of the above techniques is that it can be pretty hard to verify that your circuit is not going to miss timing. Asynchronous logic is more reliable under variable power, i.e. since it is self-timed you don't have to control a clock as well as the voltage(s) simultaneously.

Also, there's no support for describing these techniques in Verilog, so how does anyone verify this stuff, is fast-spice the only good option?
I think that he problem with asynchronous logic is that to use it requires a "boil the ocean" change. I've seen many asynchronous logic companies come and go. When I was running engineering at Ambit one would come out of the woodwork hoping to get my ear every few months (having been told by Synopsys that they could forget expecting them to change DC/PT to support asynchronous design).

The problem is simply that almost every tool needs to change. It needs a new synthesis tool, you can't use static timing (at least in the traditional sense), place and route does some logic re-synthesis so needs to be updated and so on. Then you have to test the chips and we really only have ATPG for that so we need an asynchronous version of that since you can't just switch in a test clock because there wasn't a clock there in the first place. Then there's all the IP that isn't available in asynchronous form from processors, to memories, to ethernet interfaces. And when you've done all that you have to train everyone to design asynchronously, courses in universities etc.

I think you can argue that Magma, when it started, took a new approach as to how to handle critical path timing in designs. Probably some other innovation too. But much less than a switch to asynchronous. And it took over $100M to get to market.
Having been in the asynchronous trenches myself, I totally agree with Paul McLellan's viewpoint.

For asynchronous design to achieve industrial viability it requires new EDA tools and algorithms (which may be supplementary to existing ones), which require a very significant development effort.

For example, conventional STA must be supplemented with Asynchronous STA, where the notion of critical path is substituted by the notion of critical circuit cycle. Conventional logic synthesis must be able to provide asynchronous solutions, with both (area, delay, speed) tradeoffs, and clear benefits over the synchronous equivalent. Last but not least, all back-end, timing-driven algorithms must be modified to support Asynchronous STA, as well as the conventional STA...

Last but not least, the adaptive nature of asynchronous circuits, which can certainly work in their favour, e.g. with respect to PVT variations, is also often perceived as an obstacle, as industrial designs must be shipped with specific frequency and power constraints.

Thus, it takes a significant shift of a significant portion of the Semiconductor industry to asynchronous design, to enable such as change. And this shift will probably only happen, when no other method works...
For example, conventional STA must be supplemented with Asynchronous STA...

I'm not entirely convinced that "conventional" STA copes well with power management. Either way handling asynchronous stuff is just circuits, I don't think it really qualifies as a "boil the ocean" change - i.e. if you can handle the power management circuitry properly then asynchronous logic isn't going to be hard. However, I'll give you that it will be hard if you try to fit it into the already inadequate/dysfunctional RTL flow.

Low power is always interesting to discuss. However, am not sure one can categorically nominate a particular technique as 'best' across designs and technologies. But let me try to offer my 2 cents from my experience...

Dynamic / Run power reduction: Aimed at reducing the voltage of operation. Multi-voltage designs (have multiple, and independent power grids, and supply a higher voltage to high-speed circuits only), DVFS (dynamically switch supply on the fly; increase voltage only while running highs-speed applications) and smart clock gating (use multiple clock branches, rather than a single clock. Gate off branches at source) are some examples.

Leakage reduction: Aimed at reducing leakage power. Power gating (switch off supply to circuits, when idle), Power gating while retaining state (retain state in the slave latch, and switch off supply to rest of the circuit; or save state in an on-chip RAM), using multi-Vt devices (use lower Vt devices for fast circuits only) or well biasing are some examples.

In practice, power sensitive SoC's will use one or more of the above techniques in conjunction, depending on the architecture and what makes sense for the circuit. For example, if state retention is not important, one would use plain power gating as a leakage reduction technique. It is also common to find different techniques being used for different modules in the same chip! Note that each technique is associated with some overhead that will need to factored in.
Posted by Arijit
Asynchronous Logic - One of the technologies used on the first computers - different technologies, e.g. NCL. Or the Asynchronous DLX processor implementation see opencores and . Synchronous clocking of SOCs uses 30% of the current I was told. More you can find in the Asynchronous and Synchronous Logic Group
Posted by Juergen
Killing the cut through current that exists when a power transistor's gate driver switches is a small but critical part of reducing power. The easiest way is not by using timer circuits that delay turn-on one transistor until the transistor turning off has done so, but by simply splitting the drains of the driver transistors and running a separate termination resistor from each drain to the targeted power transistor.

This little trick severely restricts the cut-through current that occurs when both transistors are briefly on. The transistor turning off will still be facing a power transistor gate whose voltage is only beginning to move away from its own source pin's voltage, thus the current through its terminating resistor will be virtually nill. There will not be these multi-amp power spikes that occur if the two drains had remained connected.

This way the terminating resistors can be tuned for the internal resistance of the P channel and N channel gate drivers, respectively.
Posted by Larry
I have been carried out power analyses in RTL design of many blocks of a SoC and I find that a lot of work can be done at RTL to reduce power consumption. Power has become one of major concerns nowadays but many blocks have been designed without awareness of power, either by the fact that they were designed long time ago where power was not a problem or the designers are not trained for low power RTL design techniques.

Among "power bugs" that I found in the design, we can mention for example a CSA circuit which is always toggled but it is not always used. Also, SRAM is an important source of power consumption but it is sometimes not optimally used and induces power wasting.

I obtained significant power reduction with this technique so I believe that power reduction at RTL design can be added in one of efficient low power techniques.
Posted by Duc-Phuong
Hi Arjit,
Thanks, but I think we have to distingush between SW features and HW implementation in silicon,
Asynchronous design is SW only and any savings in HW ccome on top.

In HW Sub Threshold is another way where possible to implement.
Posted by Juergen
Dear Juergen,

I could not agree more. I was just penning down my experience - which has predominantly been in HW techniques...
Posted by Arijit