Best Low Power techniques around !!!

[simguru]

Could you elaborate on the statement above? Why doesn't conventional STA cope with Power Management Techniques?

Thanks,

Christos.

Having sat through a presentation on low-power techniques at Mentor a while back, where it appeared that the approach to verifying the logic that was using variable supply voltages was to keep reloading different sets of SDF data. I'm assuming that most of the current tools were not designed for this use scenario and it's all a big hack.

Power management is largely an analog/mixed-signal problem, and hardly any of the EDA vendors turn up at Accellera looking for support in Verilog-AMS and definitely not in SV at the IEEE. I've had standing proposals for back-annotation and power supply hook-up for years that nobody has shown any interest in. So as far as I can tell most folks are probably just crossing their fingers until they get to the point of layout extraction and fast spice.

I could be wrong, but I would point to Wally Rhines numbers of only 30% of chips working on first pass as an indication that if the parts of the flow I know well are dysfunctional, then it's likely to be pervasive.

 

[Daniel Payne]

John,

Way back in the 1970's we were using back-biasing in NMOS technology to control the Vt and reduce capacitance of the source/drain to the bulk.

Wikipedia has a nice explanation of the body effect.

 

[LinkedIn]

Arguably the most common techniques is clock gating (CG). However, it come sin many forms. Local clock gating leverages register enables and, with the aid of synthesis tools, shuts down register clocks. RTL power reductions tools also help in this domain by identifying enable conditions for non-enabled registers so that synthesis tools can gate register clocks. RTL analysis tools also find ways to improve clock enable efficiency. Another type of CG is global CG - shutting down clocks for blocks. Advantage of CG is obviously power reduction, but clock skew management and testability become more challenging.

There are other RTL power reduction techniques such as precomputation but CG is most prevalent. In the synthesis/physical design flow, one common technique to reduce leakage power is multi-Vt cell swapping. This requires an extra mask step, so it's not really 'free', but can give 10%+ leakage power reduction with no area impact in virtually no timing impact (no WNS impact, some TNS degradation).

Power gating is turning off power supplies to blocks, and is aimed at leakage power reduction. Very big leakage power savings, but needs to be carefully implemented to avoid power integrity issues with on-rush current.

Feel free to contact me via LinkedIn if you need more details.
Posted by William

 

[LinkedIn]

Clock Gating !
clock network is the highest power consumer, and gating it once the related logic is not needed can save alot of power.
on the lowside this has impact on timing we increase Z/Capacitance to add the gating. if done in places where gating will not be activated then you paid power for nothing.
Posted by Rasheed

 

[LinkedIn]

> But these glitches cost us a lot of power.

A related problem is that the glitch power can't even be measured, or not without a lot of effort.
A digital simulator will show transitions occurring at specific times, and the timing of the transitions determine when glitches occur. The timing in the digital simulation is an estimate, and the 1->0 and 0->1 transitions have slopes, so the occurrence of glitches aren't what the simulator shows. You could simulate in spice, but then the difficulty is with simulating the whole circuit, and with activity that models real-world use.
Another alternative is to measure power in the lab, but there's no easy way to determine what the glitch power contribution is.
Is there a known good solution for measuring or estimating glitch power that isn't
based on gross estimates?
Posted by Jim

 

[LinkedIn]

the problem with glitches,is that timing tools tend to use worst case scenarios for timing while using these scenarios for power will be way of than silicion and adding silicon variation makes it almost iimpossible to "guess" real glitch numbers. gate level power analysis can indicate glitch oriented fubs, but its hard to tell where exactly thte glitch power will be consumed inside the design. so except high level guidelines I am not sure how can we fine tune for glitches power reduction
Posted by Rasheed

 

[LinkedIn]

Certain gate-level power analysis tools have a glitch power model, which has been calibrated against transistor-level analysis. Glitch power can be as low as a couple of percent up to as much as 30% in some designs. In order to compute power for glitches though, a gate level tool must have a full timing annotated (i.e. sdf annotated) gate-level simulation as an input. RTL tools, OTOH, can apply some heuristics for glitch power because they understand the design structure (e.g. multiplier, adders).
Posted by William

 

[LinkedIn]

the problem with glitches,is that timing tools tend to use worst case scenarios for timing while using these scenarios for power will be way of than silicion and adding silicon variation makes it almost iimpossible to "guess" real glitch numbers. gate level power analysis can indicate glitch oriented fubs, but its hard to tell where exactly thte glitch power will be consumed inside the design. so except high level guidelines I am not sure how can we fine tune for glitches power reduction
Posted by Rasheed

 

[LinkedIn]

> What you cannot measure cannot be controlled.

It's actually worse than that.

If you run power analysis on a gate level netlist, you will get a number for power due to glitches. However small errors in propagation delays will give you large errors in how many glitches occur. I don't have a feel for how far off the actual power will be relative to a gate level analysis with parasitics, but intuitively, it seems that the error could dominate the calculation for glitch power. The errors are compounded if one's running RTL without placement data. I don't know of any study that's looked into this measurement problem in sufficient detail to characterize the error bound (although I haven't searched recently).

So you can estimate glitch power, but the number you get will be wrong, and you can't tell how wrong it is.
Posted by Jim

 

[Tammy1949]

Yes, that is a very insightful topic.
IN coursework, we studied using lower voltages, lower leakage technologies etc. But it will be very useful to know how exactly these are implemented in the industry.

 

[tanvir]

Switching activity in the interconnects cause a lot of power consumption. Some encoding like T0 is used to avoid unnecessary switching activity on the interconnect.

 

[LinkedIn]

Motoi ICHIHASHI • Can I add a comment?

At first, I suppose we should consider which part of power consumption we want to reduce; Dynamic power or Static power, and which design level we can use.
Here, I would like to discuss the list of some "low-power" technique within the CMOS technology. (Now besides the trade off)

Dynamic power save technique:
Algorithm: State encoding, Operand isolation, Pre-computation
Physical design / RTL: Re-timing, Clock gating
Performance control: DFS
+ Voltage control: DVS, DVFS, Dual VDD, Multi power supplies
+ Variability compatibility: AVS

Static power save technique:
Algorithm: State dependent leakage reduction
Physical design / RTL: Device channel bias, Long channel standard cell optimization
Voltage control: MTCMOS, Power gating, SC-CMOS

Dynamic & static power save technique:
Physical design ./ RTL: Multi-Vt cell synthesis
+ Variability compatibility: GALS
Voltage control + Vt control: Variable threshold biasing,
+ Variability compatibility: Vt optimization

It is so sad that I can't show you the graphical list table here.
Indeed, I extracted this one from my thesis. I'm very appreciate it if you add your comments on this thread.

Thanks,

 

[LinkedIn]

The best low power design book was written by Dr. Chandrakasan and Dr. Brodersen
in 1995. They explained architectural approaches to low power long before EDA companies showed up with low power tools.
Posted by Tim

 

[Daniel Payne]

FYI - Here's the above mentioned Low-Power CMOS Design book at Amazon.com

This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.

 

[dganousis]

Isscc 2012

Look for a major announcement from AMD at ISSCC 2012 in SF about a new and very
unique way to reduce power ... it's called resonant clock mesh design. Better
performance, BIG reduction in power ... it's worth knowing about. Here's
the listing from ISSCC 2012:

3.7 Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor
V. Sathe(1), S. Arekapudi(2), A. Ishii(3), C. Ouyang(2), M. Papaefthymiou(3,4), S. Naffziger(1)
(1) AMD, Fort Collins, CO (2) AMD, Sunnyvale, CA
(3) Cyclos Semiconductor, Berkeley, CA; (4) University of Michigan, Ann Arbor, MI