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ASML reportedly has seen the first cutback in orders for EUV equipment from TSMC, its largest customer, which market insiders speculate is on track to slash such orders by over 40% or otherwise delay taking shipments from the Dutch supplier along with its slowing fab capacity expansions in...
www.digitimes.com
ASML reportedly has seen the first cutback in orders for EUV equipment from TSMC, its largest customer, which market insiders speculate is on track to slash such orders by over 40%
2. TSMC is not going to cut/push out 40% of their N3/N2 family capex
3. N3E may have lower EUV requirements and N2 without BSPD will probably be a lower volume node (in a similar vein to N3). However I can’t imagine they can cut/push out 40% of their EUV tools when N3 family demand is so high/the phases of fab18 that will do N3 family aren’t even fully operational yet. Doubly so with N2 which has no HVM capacity built out yet if memory serves.
2. TSMC is not going to cut/push out 40% of their N3/N2 family capex
3. N3E may have lower EUV requirements and N2 without BSPD will probably be a lower volume node (in a similar vein to N3). However I can’t imagine they can cut/push out 40% of their EUV tools when N3 family demand is so high/the phases of fab18 that will do N3 family aren’t even fully operational yet. Doubly so with N2 which has no HVM capacity built out yet if memory serves.
Digitimes does have well-deserved click-bait reputation. In addition to the reasoning @nghanayem stated, it also seems unlikely that TSMC would grant such an obvious opening to Intel to grab a bunch of EUV production slots, and reduce the gap they have. It's been widely reported and discussed here that Intel suffers from a lack of EUV equipment.
Probably a 0%. At most a 20% push out (not cut) if N2 is delayed (fat chance), and N3E DDs struggle to go from good to excellent and customers push out their orders as a result (which also doesn’t seem to be the case).
Furthermore TSMC builds out capacity on wafer agreements. Given these are binding contracts customers have to buy what they ordered. For this reason there shouldnt be any reason to cut or push out production because the business is gatunteed (to say nothing of TSMC being legally obliged to fulfill it in the required time period). The only underutilization TSMC seems to have is with N7 family because of how Samsung can come in from above and below at lower costs with 8LPP and 7LPP. Given that there is no planned expansion for the N7 family at this time there isn’t really much impudence for TSMC EUV demand to drop from N7 family (and most of that isn’t even EUV for the time being).
ASML reportedly has seen the first cutback in orders for EUV equipment from TSMC, its largest customer, which market insiders speculate is on track to slash such orders by over 40% or otherwise delay taking shipments from the Dutch supplier along with its slowing fab capacity expansions in...
www.digitimes.com
ASML reportedly has seen the first cutback in orders for EUV equipment from TSMC, its largest customer, which market insiders speculate is on track to slash such orders by over 40%
Not at all. The idea that TSMC would allow Intel to get back into the EUV game just like that is ludicrous. It makes all the strategic sense in the world for TSMC to maintain orders, even if they aren’t going to use all of them right away. Cutting EUV orders right now would be an own goal of epic proportions for TSMC. I find it hard to believe management would be so short sighted
No. There is no way that tool would cause such a massive shakeup with their process flow/capex. For one it is not a silver bullet replacement for EUV. It seems to fulfil a similar role to CMP (defect density reducer), and in specific scenarios it might allow you to get away with single exposure when you might have needed LELE. Additionally TSMC would almost certainly have had preview/prototype access to it long before AMAT announced it to Wall-Street/the general public.
40% cut seems excessive, if true might this actually mean an alternative to EUV in HVM?
Given there has not been a single IEEE paper that indicates there is anything better than complex DUV multipatterning and EUV single/multi patterning, I severely doubt that.
Not at all. The idea that TSMC would allow Intel to get back into the EUV game just like that is ludicrous. It makes all the strategic sense in the world for TSMC to maintain orders, even if they aren’t going to use all of them right away. Cutting EUV orders right now would be an own goal of epic proportions for TSMC. I find it hard to believe management would be so short sighted
I think this angle is overstated. If for some reason we were to assume that TSMC did not project needing 40% of their current leading edge capex:
In my Jr. engineer opinion it would make sense to axe or push out orders. Doing so would not magically allow intel to double their 20/18A ramp volume, nor would it allow IFS to steal a bunch of TSMC business (after all TSMC would be cutting orders because there is not enough demand). Put another way I would have to assume intel's current shell build out pace is not that much faster than their ability to fund/install EUV and non EUV tools (but I suppose I could certainly be wrong here). Ian Curtis has mentioned that EUV tools took like 6mo to install and 6mo to qualify. If we were to assume this is true, and that intel bought every tool TSMC pushed out, then these tools wouldn't be ready to begin ramping until 18A or intel next. It should also not have any impact on intel's R&D efforts.
Finally where would ASML even install these tools if TSMC didn't axe/push out their orders? If you were pushing out EUV orders presumably you would also be pushing out fab shells. If that was being done where would these tools go? You can't put them in old fabs without reducing their capacity, and you would still need to wait in line for ASML to reinstall them in new fabs once the new shells were built. If alternatively TSMC decided to build 1.7x the capacity that they actually needed and were only operating at 60% utilization that would be a tank gross margins by double digit percent and take a loss on leading nodes level disaster.
Apart from the actual impact of the technology(either it's really powerful or not), Foundries can't change processes that fast. Massive changes in design rules will break businesses.
Not at all. The idea that TSMC would allow Intel to get back into the EUV game just like that is ludicrous. It makes all the strategic sense in the world for TSMC to maintain orders, even if they aren’t going to use all of them right away. Cutting EUV orders right now would be an own goal of epic proportions for TSMC. I find it hard to believe management would be so short sighted
