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Passing gates have at times been used to provide isolation between access transistors on DRAM. The rationale has been that a regular grid of gates promotes ideal lithography and if every 3rd gate is held "off" then the other 2 gates in the saddle are isolated as required.
The alternative design is an actual cut in the access channel in that same position so that the saddle channel with its two gates is isolated.
It seems that a passing gate design would make sense for SADP or SAQP with DUV but a true cut might be a reason for / benefit of using EUV in DRAM?
Fred is a way better person for this question given his litho and DRAM expertise. But my understanding of SAxP is that they don't work super great for that. If I use x to be a cut, | to be gates, and bolded lines to show features from the same core...
SADP: | | | | | | (poly post pitch doubling) | | x | | x (my understanding is you would need another SADP pass to do the cuts as well as making sure you had good alignment to make sure you don't leave any behind)
SAQP: | | | | | | | | | | | | (poly post pitch quartering) (also notice the single vs double spaces that exist for SAQP) | | x | | x | | x | | x (because the core-core spacing is different then the spacing between the quartered features I don't think this goofy offset is compatible with dram or potentially even logic. Additionally the cuts are being made at different spacing so you would need even more than just one SAQP pass to the cuts. 1st, 2nd, and 3rd cut in this example are 6 spaces apart while the 4th is only 5 away from the 3rd cut.)
SALELE: | | | | | | (poly pre spacer) (also note for SALELE since there is not pitch multiplication every feature has a unique origin. In other words features 1 and 3 are not related.) | | x | | x (The SALELE example places the cut with fewer layers than SADP because the space between cuts while similar to SADP has the benefit of spacer partially self aligning the cut where you need it to go rather than needing tight overlay in the SADP/SAQP examples or even tighter overlay needed for LE^x).
Passing gates have at times been used to provide isolation between access transistors on DRAM. The rationale has been that a regular grid of gates promotes ideal lithography and if every 3rd gate is held "off" then the other 2 gates in the saddle are isolated as required.
The alternative design is an actual cut in the access channel in that same position so that the saddle channel with its two gates is isolated.
It seems that a passing gate design would make sense for SADP or SAQP with DUV but a true cut might be a reason for / benefit of using EUV in DRAM?
The active area is already cut in the same position, do you mean to cut the buried word line? Then the word line has to be strapped close to the tall capacitor.
Gate rounding and gate cut rounding preclude any advantage for EUV.
Fred is a way better person for this question given his litho and DRAM expertise. But my understanding of SAxP is that they don't work super great for that. If I use x to be a cut, | to be gates, and bolded lines to show features from the same core...
SADP: | | | | | | (poly post pitch doubling) | | x | | x (my understanding is you would need another SADP pass to do the cuts as well as making sure you had good alignment to make sure you don't leave any behind)
SAQP: | | | | | | | | | | | | (poly post pitch quartering) (also notice the single vs double spaces that exist for SAQP) | | x | | x | | x | | x (because the core-core spacing is different then the spacing between the quartered features I don't think this goofy offset is compatible with dram or potentially even logic. Additionally the cuts are being made at different spacing so you would need even more than just one SAQP pass to the cuts. 1st, 2nd, and 3rd cut in this example are 6 spaces apart while the 4th is only 5 away from the 3rd cut.)
SALELE: | | | | | | (poly pre spacer) (also note for SALELE since there is not pitch multiplication every feature has a unique origin. In other words features 1 and 3 are not related.) | | x | | x (The SALELE example places the cut with fewer layers than SADP because the space between cuts while similar to SADP has the benefit of spacer partially self aligning the cut where you need it to go rather than needing tight overlay in the SADP/SAQP examples or even tighter overlay needed for LE^x).
Nice paper! It changed my understanding of passing gates. In some older designs I had seen the access channels terminated by dummy gates which were always-off, and I thought that was what passing-gates are. Now I see what you mean "the active area" - access channel - "is already cut in the same position". So the word lines are put down after that and then every 3rd crossing is a "passing gate".
