DDR5 DIMMs have 1 channel per 8 chips. LPDDR5 has a channel for each chip. DRAM core arrays are closely similar in each generation from each manufacturer, but the whole point of DDR, LPDDR, GDDR, HBM, is the different interfaces wrapped around the arrays for different tradeoffs when interfacing to the host. Apple has doubled down on extracting the performance potential of LPDDR, which explains a lot of their power/perf advantage.
Servers typically have around 8GB per dual-thread core. The M2 Ultra has 8GB per single-thread, though it is sharing with a GPU (like future servers will need to do, as inferencing becomes ubiquitous). The remaining difference is RAS. I expect the next generation of LPDDR will go beyond single bit correction and provide better probity, at which DDR may lose a lot of its market share.