Intel's Foundry Business discloses a $7B operating loss

[blueone]

KEY POINTS

• - Intel shares fell more than 4% in extended trading on Tuesday after the company revealed long-awaited financials for its semiconductor manufacturing business, commonly called the foundry business, in a SEC filing.
• - This is the first time that Intel has disclosed how much its foundry business makes in sales.

Intel discloses $7 billion operating loss for chip-making unit

Intel plans to spend $100 billion on building or expanding chip factories in four U.S. states.

www.cnbc.com

I can't say I'm surprised.

 

[Daniel Nenni]

(Reuters) -Intel on Tuesday disclosed deepening operating losses for its foundry business, a blow to the chipmaker as it tries to regain a technology lead it lost in recent years to Taiwan Semiconductor Manufacturing .

https://www.intc.com/filings-reports/all-sec-filings/content/0000050863-24-000068/0000050863-24-000068.pdf

Intel said the manufacturing unit had $7 billion in operating losses for 2023, a steeper loss than the $5.2 billion in operating losses the year before. The unit had revenue of $18.9 billion for 2023, down 31% from $63.05 billion the year before.

Intel shares were down 4.3% after the documents were filed with the U.S. Securities and Exchange Commission (SEC).

During a presentation for investors, Chief Executive Pat Gelsinger said that 2024 would be the year of worst operating losses for the company's chipmaking business and that it expects to break even on an operating basis by about 2027.

Gelsinger said the foundry business was weighed down by bad decisions, including one years ago against using extreme ultraviolet (EUV) machines from Dutch firm ASML. While those machines can cost more than $150 million, they are more cost-effective than earlier chip making tools.

Partially as a result of the missteps, Intel has outsourced about 30% of the total number of wafers to external contract manufacturers such as TSMC, Gelsinger said. It aims to bring that number down to roughly 20%.

Intel has now switched over to using EUV tools, which will cover more and more production needs as older machines are phased out.

"In the post EUV era, we see that we're very competitive now on price, performance (and) back to leadership," Gelsinger said. "And in the pre-EUV era we carried a lot of costs and (were) uncompetitive."

Intel plans to spend $100 billion on building or expanding chip factories in four U.S. states. Its business turnaround plan depends on persuading outside companies to use its manufacturing services.

As part of that plan, Intel told investors it would start reporting the results of its manufacturing operations as a standalone unit. The company has been investing heavily to catch up to its primary chipmaking rivals, TSMC and Samsung Electronics Co Ltd .

Intel discloses $7 billion operating loss for chip-making unit

(Reuters) -Intel on Tuesday disclosed deepening operating losses for its foundry business, a blow to the chipmaker as it tries to regain a technology lead it lost in recent years to Taiwan Semiconductor Manufacturing . Intel said the manufacturing unit had $7 billion in operating losses for...

www.yahoo.com

 

[MKWVentures]

We published a blog on this and how it matches the scenarios we published on Semiwiki last month
Key takeaway: Intel Costs are higher than TSMC price. Intel is now talking about a longer turnaround time and slower process ramps than some people believed.
One key disagreement with Pat. Its not like the Fab cost problem started with 10nm++++ (Intel 7). Intel needs structural changes in operations and volume to be cost effective. This was true on 22nm, 14nm etc as well. The difference then was that Intel had no competition. See our website for more details www.mkwventures.com

 

[Mooredaddy]

Yikes

 

[Daniel Nenni]

Here is the transcript from the webinar:

Intel Corporation (INTC) New Segment Reporting Webinar (Transcript)

Intel Corporation (NASDAQ:NASDAQ:INTC) New Segment Reporting Webinar Conference April 2, 2024 4:30 PM ETCompany ParticipantsJohn Pitzer - Corporate Vice...

seekingalpha.com

And here is the filing:

https://www.intc.com/filings-report...0000050863-24-000068/0000050863-24-000068.pdf

Press release:

Intel Outlines Financial Framework for Foundry Business, Sets Path to Margin Expansion

www.intc.com

Intel is changing accounting practices which brings more transparency. Hopefully the Intel board knew all of this when they signed off on the whole IDM 2.0 strategy otherwise there could be problems.

Presentation:

https://d1io3yog0oux5.cloudfront.net/_9bece0e2e2052ad835960ec926e1b746/intel/db/856/8992/presentation/Intel+New+Segment+Reporting+Webinar+-+for+posting+to+INTC.com.pdf

Infographic:

https://download.intel.com/newsroom/2024/corporate/resegmentation-infographic.pdf

 

[Daniel Nenni]

This is the most interesting slide. The dash means Intel is behind, the squiggles means Intel is comparable and plus means ahead. They don't say who the comparison is with but clearly it is TSMC. They key here is the Target Segment, so this is in terms of HPC. As far as performance goes I agree with this graphic but not performance per watt. I have a problem with wafer cost especially when yield is involved. I also do not agree with the 18A density comparison, if we are talking about TSMC. Samsung 2nm maybe, TSMC N2 no. EDA ease of use I can agree with since Intel is a big EDA customer but TSMC has the biggest EDA/IP ecosystem. Packaging is still a wait and see for me. Intel and Samsung are not doing packaging HVM for foundry customers as of yet in comparison to TSMC. On paper maybe but foundry HVM is a different deal altogether.

 

[blueone]

This is the most interesting slide. The dash means Intel is behind, the squiggles means Intel is comparable and plus means ahead. They don't say who the comparison is with but clearly it is TSMC. They key here is the Target Segment, so this is in terms of HPC. As far as performance goes I agree with this graphic but not performance per watt. I have a problem with wafer cost especially when yield is involved. I also do not agree with the 18A density comparison, if we are talking about TSMC. Samsung 2nm maybe, TSMC N2 no. EDA ease of use I can agree with since Intel is a big EDA customer but TSMC has the biggest EDA/IP ecosystem. Packaging is still a wait and see for me. Intel and Samsung are not doing packaging HVM for foundry customers as of yet in comparison to TSMC. On paper maybe but foundry HVM is a different deal altogether.

View attachment 1809

It would be incredibly fascinating if TSMC personnel made a version of this slide with their scoring of the Intel nodes. I know it'll never happen, but it would be fascinating.

 

[Scotten Jones]

This is the most interesting slide. The dash means Intel is behind, the squiggles means Intel is comparable and plus means ahead. They don't say who the comparison is with but clearly it is TSMC. They key here is the Target Segment, so this is in terms of HPC. As far as performance goes I agree with this graphic but not performance per watt. I have a problem with wafer cost especially when yield is involved. I also do not agree with the 18A density comparison, if we are talking about TSMC. Samsung 2nm maybe, TSMC N2 no. EDA ease of use I can agree with since Intel is a big EDA customer but TSMC has the biggest EDA/IP ecosystem. Packaging is still a wait and see for me. Intel and Samsung are not doing packaging HVM for foundry customers as of yet in comparison to TSMC. On paper maybe but foundry HVM is a different deal altogether.

View attachment 1809

This is an interesting slide:
- Performance/watt - I agree with their ratings.
- Density - I don't agree with, TSMC is way ahead of 18A, maybe Intel could catch up at 14A but it would take a huge jump.
- Wafer cost - surprisingly, I was just looking at wafer cost and through 18A I think they are correct, I need to look at 14A some more, maybe it will be a plus if they bet right on High NA and TSMC bet wrong.
- I don't really have an opinion on the bottom 3 lines.

 

[nghanayem]

This is the most interesting slide. The dash means Intel is behind, the squiggles means Intel is comparable and plus means ahead. They don't say who the comparison is with but clearly it is TSMC.

They said they were comparing to the best node on the market at the time. Given ICL launched at EOY 2019 and TGL at EOY 2020, and they said intel 7 was far behind on density and performance it is pretty clear they are comparing to N5 family not N7. Density wise intel 4 trades blows with N5 family so clearly they must be comparing intel 3 to N3E family. For 18A they mentioned that it would beat the node they were comparing to market. I suppose that could theoretically be N3P, but that statement reads more like N2 to me.

The key here is the Target Segment, so this is in terms of HPC. As far as performance goes I agree with this graphic but not performance per watt.

Performance per watt at 1.2V is very different beast from PPW at Vmin. If we are talking about HPC only (which is what intel markets 18A non P as then I would assume PPW at high power is what they are talking about). IMO performance with no power constraints is a worthless metric. For CCG, sure it is important. But for HPC foundry or DCAI they want PPW not raw performance. If we want to talk about performance with unconstrained power intel 7 then I suppose you could say that it is the best node ever, and runs laps around N3. Of course no matter who you work for, you would rightfully laugh me out of the room if I said something so ignorant. For this reason I think it is important to delineate high vs low V PPW. Or maybe using the term power-performance to talk about low power PPW?

I have a problem with wafer cost especially when yield is involved.

How so? Yield is yield, wafer cost is wafer cost. Yield can be improved to some asymptotic limit. Long term wafer cost post process ramp/depreciation is mostly determined by process flow decisions (i.e. you are stuck with it forever whereas yield is transient/evolving).

This is an interesting slide:
- Density - I don't agree with, TSMC is way ahead of 18A, maybe Intel could catch up at

Interesting... prior recent projections I saw from you guys put 18A and N3 pretty close together (but maybe my brain is too heavily calibrated to the traditional 1.8-2X per node). As for N3-->N2 my assumption was that almost all of that 15% area improvement quoted is from the HD cell getting smaller than the N3E 2 fin device and all N2 devices being this way rather than what you have with N3 where only half of the devices are that 1 fin device. Put another way, on a theoretical basis (imperfect measurement, I know) the gap from 18A to N2 doesn't feel like it would be in "way ahead" territory. That is unless you mean by the standards of the difference is really big considering they are both 2"nm" class nodes and there is a big difference between them, rather than TSMC being 1.8-2X ahead. Although maybe this "way ahead" coming from a more nuanced definition of density in a more product like environment? If so I wonder if the high std cell utilization shown off by intel on intel 4+powervia will have real world density implications in excess of the theoretical improvement you see from reducing the number of M0 tracks? If things do pan out that way, then I have to assume that N2+BSPD can be an even bigger monster than I already think it could be.

maybe Intel could catch up at 14A but it would take a huge jump.

Do your projections match up with their claim if we assume they are comparing 14A to N2+BSPD given that it feels like 2027 14A sounds to be slotting between N1.4 and that?

 

[hist78]

This is the most interesting slide. The dash means Intel is behind, the squiggles means Intel is comparable and plus means ahead. They don't say who the comparison is with but clearly it is TSMC. They key here is the Target Segment, so this is in terms of HPC. As far as performance goes I agree with this graphic but not performance per watt. I have a problem with wafer cost especially when yield is involved. I also do not agree with the 18A density comparison, if we are talking about TSMC. Samsung 2nm maybe, TSMC N2 no. EDA ease of use I can agree with since Intel is a big EDA customer but TSMC has the biggest EDA/IP ecosystem. Packaging is still a wait and see for me. Intel and Samsung are not doing packaging HVM for foundry customers as of yet in comparison to TSMC. On paper maybe but foundry HVM is a different deal altogether.

View attachment 1809

Where is the Intel 20A in this slide? Did Intel decide to kill/skip it?

With the introduction of 14A and its technical superiority, does that mean Intel push the year of gaining leadership position over TSMC further down to a future date?

 

[Fred Chen]

Gelsinger said the foundry business was weighed down by bad decisions, including one years ago against using extreme ultraviolet (EUV) machines from Dutch firm ASML. While those machines can cost more than $150 million, they are more cost-effective than earlier chip making tools.

Partially as a result of the missteps, Intel has outsourced about 30% of the total number of wafers to external contract manufacturers such as TSMC, Gelsinger said. It aims to bring that number down to roughly 20%.

Intel has now switched over to using EUV tools, which will cover more and more production needs as older machines are phased out.

"In the post EUV era, we see that we're very competitive now on price, performance (and) back to leadership," Gelsinger said. "And in the pre-EUV era we carried a lot of costs and (were) uncompetitive."

Gelsinger is using the old strawman of "no EUV" to blame for Intel falling behind (in process release leadership) when actually it was their entire 10nm execution. They were still ahead at 14nm. Now that it's acknowledged that Intel 10nm is actually to be compared to TSMC N7, we see it's really not about use of EUV but the lack of flexibility in their execution (e.g., Co interconnect). The "post-EUV" era just starting now with Intel 4 is mixed with the introduction of chiplets, so that leadership is now very dependent on external foundries in general.

 

[tooLongInEDA]

One of the interesting points (from the long call transcript) for me was the discussion about Intel's heavy historical use of "expedites" (I take that to mean fast, very low volume lots for respins, testchips, early tapeouts, etc). They are saying this was a significant factor in their historic fab inefficiency/high cost - that they didn't charge enough for this service and that it signifcantly disrupted regular production. Makes some sense.

So fab efficiency and wafer cost can get a one-off improvement by fixing this.

But what happens to the design/product side of the business, now they don't get a free ride on respins from the fabs ? Presumably they have to rethink their approach and use less respins (apparently "steppings" in Intel speak). But I guess the 30% of wafers (30% of designs ?) currently going through TSMC already have to face this challenge.

The new IFS accounting certainly makes the fab business look very inefficient and the design/product side more profitable than we might have assumed. But perhaps the required fab savings will result in some cost increases on the product side.

 

[lefty]

Intel could have made the $7 billion number much lower just by paying itself more money for IFS services.

 

[nghanayem]

The new IFS accounting certainly makes the fab business look very inefficient and the design/product side more profitable than we might have assumed.

Agreed, I knew there would be a loss but I had assumed it would be more minor than what it is. But seeing the 2022/21 data I suppose there is at least some sollice in about a third of the operating loss being due to fabs being underutilized because intel overshot their product demand projections. Alot of the cost also seems to also just be the lost scale. They said they planned to bring back 2 whole mods of stuff back from TSMC, enough to fill a whole F38/48 on its own. Additionally the cost of 5N4Y TD, plus ramping 2 process technology families in parallel, and adding 12 fabs to their off the top of my head count of the current 14. I think the thing that was most interesting is how alot of getting to profitability was not really relying on external really at all. Which is a good start.

Either way cost is now a concern going forward to the foundry era since the incentive structure has now changed. Everything was getting obfuscated behind margin stacking and it would have been harder to see the issues. Double that with what the old mission charter was. Be the best capacity source for our high margin CPUs. If that is what you are doing your measurable objectives will mainly be TTM and PPA so you can commend the highest price. I made a point in this vain before with AMD vs intel, where it almost was irrelevant what something like intel 32nm costed vs GF 32nm SOI because intel would be on 22nm by then and any cost per wafer @iso process deficit is more than made up by being further along the Moore cost curve. You see this in intel's margins when they had a huge process lead and as a result cost and performance leadership being higher than a QCOM+TSMC and WAAAAY higher than an AMD+GF. Now that the "product" is the wafers not the CPUs on the wafers the incentive structure for manufacturing is different.

But perhaps the required fab savings will result in some cost increases on the product side.

That it did.

BU OM improvements come with a GM degradation. They no longer need to pay for the operations of the fabs, TD, fab buildouts, and ramp costs. But now their wafers/packaging are more expensive because they don't just get them for "free". Although saying that intel 7 is seemingly being given close to cost even charging at the "fair market value" (which in my opinion is around N6). Proving the idea that intel 7 was not cost competitive even if it was PPA competitive with N7 family. Since both N7 and intel 7 are underutilized that also seems to make the comparison even more like for like since the utilization can increases the wafer cost.

Intel could have made the $7 billion number much lower just by paying itself more money for IFS services.

If your goal is to make the organization healthy and fix systemic issues why would you do that? Sure if your goal was to pump and dump it on an IPO, why not say prod co is the one running at a loss. But that would be 1) shady/maybe illegal, 2) not in line with the IDM2.0 vision of having two strong halves that margin stack to make 1 super profitable intel corp. To do that Products needs to at least get on AMDs level and aspire to get to NVIDIA's level. Foundry needs to get to profitability first (as I stated the second they are profitable then the Intel's IDM has been fixed and they are seeing the benefits of being one company again), then get to normal foundry like margins for them to be a huge success. To get there you need to be honest where the challenges are, identify the solutions as intel as and go and fix them.

Where is the Intel 20A in this slide? Did Intel decide to kill/skip it?

TSMC doesn't break out N4 vs N5 they keep it all in an N5 bucket. Why would intel break out a pipecleaner process like intel 4/20A into their financials if they are financially insignificant beyond being the main volume during ramp?

With the introduction of 14A and its technical superiority, does that mean Intel push the year of gaining leadership position over TSMC further down to a future date?

The leadership position they have talked about has been stated many times to be leadership in so far as it pertains to performance per watt. They still claim that they think 18A will have it, and that they believe they will beat "its competition" to market. So no, intel hasn't just admitted failure in this regard. Granted they've got around a year to go so time will if they make good on said promise.

 

[blueone]

But what happens to the design/product side of the business, now they don't get a free ride on respins from the fabs ? Presumably they have to rethink their approach and use less respins (apparently "steppings" in Intel speak). But I guess the 30% of wafers (30% of designs ?) currently going through TSMC already have to face this challenge.

Chiplets make this problem less critical. You don't need to re-spin a huge monolithic chip every time a single block may have a design flaw. And some flaws will keep other blocks from being properly tested, so you can get into re-spin scenarios that are the sum of the block-level errors. GPUs have more monolithic designs than client CPUs (fewer unique circuits per unit die area), so Nvidia has an inherent advantage with very large single dies.

The new IFS accounting certainly makes the fab business look very inefficient and the design/product side more profitable than we might have assumed. But perhaps the required fab savings will result in some cost increases on the product side.

Only because IFS has so little revenue to cover the build-out ramp. The foundry business also has more risk due to far higher CapEx investments.

 

[lefty]

I notice IFS loss was around $5 billion for both 2022 and 2021 - that is despite Intel making $12 billion less revenue in 2022. Really IFS loss should be more for 2022, because they are manufacturing less products.

 

[blueone]

Last night I saw something on LinkedIn which concerned me more than the big loss, which I expected given the change in accounting and the huge investments Intel is making. This job posting:

Intel Corporation hiring Corporate Vice President and DCAI Chief Architect in Santa Clara, CA | LinkedIn

Posted 3:33:33 PM. Job DescriptionAbout Data Center and AI: The exponential growth of data and some of the fastest…See this and similar jobs on LinkedIn.

www.linkedin.com

Seriously? At this juncture Intel is first worried about hiring a data center AI chief architect at the corporate VP level? (For those who don't know, corporate VPs are the lowest level corporate officers, but this is a very senior position. Most VPs by population in Intel are what's called "appointed VPs", and they're not corporate officers.) Corporate VPs are at least what Intel calls Grade 13 employees, so we're probably talking cash compensation over $1.5M, especially with a job description like this. No one at this level gets hired without CEO approval. And, shockingly, this obviously isn't a retained search. (Retained searches are where companies hire top-gun industry recruiters like Korn Ferry or Heidrick and Struggles to do very targeted and secret recruiting.) This is just an open posting on LinkedIn. I'm amazed. (Notice that they already have 40 applicants.) This is just advertising a big leadership hole. I also doubt any serious candidates are just going to apply to a LinkedIn posting.

 

[lefty]

I think next year IFS will lose even more money. By then probably 50% client processors sold will be Meteor lake / Arrow lake and both these processors are mostly manufactured by TSMC. Intel's external customers are all low volume, so Intel's fabs will be mostly idle.

 

[nghanayem]

I notice IFS loss was around $5 billion for both 2022 and 2021 - that is despite Intel making $12 billion less revenue in 2022. Really IFS loss should be more for 2022, because they are manufacturing less products.

Yeah I thought that was weird too. Only guess I have as to why is that D1X mod 3 finished and Fab34 finished so they would have been installing new tooling for those? Could also be related to increased to getting to a more expensive phase of TD?

 

[Daniel Nenni]

Here is Ian Cutress's take on it:

Intel Foundry: Realigning the Money

Full transition to Foundry revenues vs Product

morethanmoore.substack.com

Not 100% correct but very good for an outsider. I have been following Ian since he wrote at Anandtech. I see him at semiconductor events. He covers EDA now as well and was at the Synopsys User Group Meeting last month.