Intel's Foundry Business discloses a $7B operating loss

[MKWVentures]

Intel Cost is a lot higher than TSMC price. Intel cost is 2x TSMC cost for similar technology. They plan to fix this somewhere between 2027 and 2030. We can discuss the details why but it is not just the technology in and of itself. The main issue is Production (wafers sold) output per tool. There are things Intel is working on to fix this but there are other items that are difficult to change

 

[MKWVentures]

One of the interesting points (from the long call transcript) for me was the discussion about Intel's heavy historical use of "expedites" (I take that to mean fast, very low volume lots for respins, testchips, early tapeouts, etc). They are saying this was a significant factor in their historic fab inefficiency/high cost - that they didn't charge enough for this service and that it signifcantly disrupted regular production. Makes some sense.

So fab efficiency and wafer cost can get a one-off improvement by fixing this.

But what happens to the design/product side of the business, now they don't get a free ride on respins from the fabs ? Presumably they have to rethink their approach and use less respins (apparently "steppings" in Intel speak). But I guess the 30% of wafers (30% of designs ?) currently going through TSMC already have to face this challenge.

The new IFS accounting certainly makes the fab business look very inefficient and the design/product side more profitable than we might have assumed. But perhaps the required fab savings will result in some cost increases on the product side.

the issue isnt thought to be the product side. The product groups expect to save tons of money with TSMC and get product support. This is why they are breaking the costs out so the product groups doesnt take the profit hit for using Intel Fab.

 

[blueone]

I still don't understand how Intel gets a wafer cost advantage at 14A over TSMC.

 

[MKWVentures]

One other item. I think the biggest issue from the webinar (since we knew Intel Costs are higher than TSMC price) is the timelines. Multiple comments referred to ramps much slower than expected, cost reductions much slower, timelines out to 2030. This is all before the fab delays are announced. Intel is looking at the scenarios now but the pressure on Pat's optimism will intensify.

 

[nghanayem]

Intel Cost is a lot higher than TSMC price. Intel cost is 2x TSMC cost for similar technology. They plan to fix this somewhere between 2027 and 2030. We can discuss the details why but it is not just the technology in and of itself. The main issue is Production (wafers sold) output per tool. There are things Intel is working on to fix this but there are other items that are difficult to change

If intel's cost per wafer is 2x than TSMC, the cost of goods sold literally can't increase for product side like it did. If cost was even 1% greater than price COGS would go down. Later on they even say they are charging about 0% margin for intel 7 vs N5 wafer price. So let's call 10nm cost = N5 price, N5 price is not more than 2x TSMC cost. TSMC says N7 is dragging TSMC margins down due to low utilization so they clearly aren't doing better than N5 margins on N7. N7, margins would need to be like 70-90% for intel's cost to be 2x N7 cost (assuming a 10-30% cost per wafer increase for N5), and there is simply no indication that N7 is even 60% since they litterally said it drags their margins down and they are at 53%.

 

[hist78]

Intel could have made the $7 billion number much lower just by paying itself more money for IFS services.

"Intel said its foundry business recorded an operating loss of $7 billion in 2023 on sales of $18.9 billion. That’s a wider loss than the $5.2 billion Intel reported in its foundry business in 2022 on $27.5 billion in sales."

"Intel said the newly organized Products division, which mainly consists of processors for PCs and servers, reported $11.3 billion in operating income on $47.7 billion in sales in 2023."

In the real world, the Intel Corp. has only one accounting book and one stock symbol, INTC, and one stock price. The super majority of Intel Foundry's revenue, cost, and profit are coming from Intel Product division's orders. Is Intel Foundry really that bad? Or it's just because Intel Product division can't design and sell the right products with the the right price at the right time? Or Intel Foundry is used as a scapegoat to masquerade the lacking competitiveness of Intel products?

Intel pushed/allocated more cost to Intel Foundry to make people think Intel Product division is still shining, IMO.

The goal is to keep Intel stock price high and buy time for regaining technology leadership.

 

[MKWVentures]

If intel's cost per wafer is 2x than TSMC, the cost of goods sold literally can't increase for product side like it did. If cost was even 1% greater than price COGS would go down. Later on they even say they are charging about 0% margin for intel 7 vs N5 wafer price. So let's call 10nm cost = N5 price, N5 price is not more than 2x TSMC cost. TSMC says N7 is dragging TSMC margins down due to low utilization so they clearly aren't doing better than N5 margins on N7. N7, margins would need to be like 70-90% for intel's cost to be 2x N7 cost (assuming a 10-30% cost per wafer increase for N5), and there is simply no indication that N7 is even 60% since they litterally said it drags their margins down and they are at 53%.

I have already broken out the margin impact in a spreadsheet. the numbers for Intel add up. We can set up a meeting to review the specifics. Intel is buying TSMC today and Intel has used Intel in the past so Intel knows the costs

 

[VCT]

Intel claimed 18A wafer cost as good as TSMC:
Question:
1. Intel use 8-year depreciation while TSMC use 5-year depreciation
2. Intel assume production yield as good as TSMC. We know it won't happen.
3. Intel assume Fab utilization rate as good as TSMC which is difficult consider TSMC build the Fab after customer commitment and Intel don't.

On paper, theoretically, UMC's cost should be similar to TSMC cost. But it never happened in the past 30 years.
UMC shares more similarities with TSMC than Intel does with TSMC.

 

[tooLongInEDA]

Intel claimed 18A wafer cost as good as TSMC:
Question:
1. Intel use 7-year depreciation while TSMC use 5-year depreciation
2. Intel assume production yield as good as TSMC. We know it won't happen.
3. Intel assume Fab utilization rate as good as TSMC which is difficult consider TSMC build the Fab after customer commitment and Intel don't.

Interesting - this is the sort of thing you'd hope the Wall Street analysts on the call might have queried, but .... . The increased Intel depreciation change is still quite recent. isn't it ? I read somewhere it was 8 years ? Also worth noting that until it reaches breakeven, Intel has far less scope for price reductions than TSMC.

And that demand and pricing downturns are a thing in the IC market. The real litmus test of all this Intel/CHIPS Act stuff is whether the US is prepared to keep going through a serious downturn.

 

[VCT]

Interesting - this is the sort of thing you'd hope the Wall Street analysts on the call might have queried, but .... . The increased Intel depreciation change is still quite recent. isn't it ? I read somewhere it was 8 years ? Also worth noting that until it reaches breakeven, Intel has far less scope for price reductions than TSMC.

And that demand and pricing downturns are a thing in the IC market. The real litmus test of all this Intel/CHIPS Act stuff is whether the US is prepared to keep going through a serious downturn.

You are right. thank you for correcting me.
Intel is 8-year while UMC is 7-year.

The difference between 8-year and 5-year depreciation is huge.

 

[Scotten Jones]

We published a blog on this and how it matches the scenarios we published on Semiwiki last month
Key takeaway: Intel Costs are higher than TSMC price. Intel is now talking about a longer turnaround time and slower process ramps than some people believed.
One key disagreement with Pat. Its not like the Fab cost problem started with 10nm++++ (Intel 7). Intel needs structural changes in operations and volume to be cost effective. This was true on 22nm, 14nm etc as well. The difference then was that Intel had no competition. See our website for more details www.mkwventures.com

When comparing wafer costs there are two components, one is process cost and the other is fab cost. Intel 10/7 processes are very expensive processes compared to TSMC 7nm even if run in the same fab. Intel fabs are generally in higher cost countries plus Intel has some Intel specific cost disadvantages. The net of this is Intel 10/7 cost is similar to TSMC selling price. The interesting thing is 18A as a process run in the same fabs as TSMC 2nm is actually a lower cost process, 18A is lower density and needs less EUV layers. Intel still has Fab cost issues but the cost to run 18A in Arizona Fab 52 versus TSMC 2nm in Fab 20-P1 is well below TSMC selling price. It is lower density but better raw performance so it depends on your needs.

Also, for the record all my wafer costs are calculated using the commercial models I sell that calibrate to published financials and inputs from a huge customer base. When I compare companies I always us the same depreciation rates to make it consistent.

 

[Scotten Jones]

They said they were comparing to the best node on the market at the time. Given ICL launched at EOY 2019 and TGL at EOY 2020, and they said intel 7 was far behind on density and performance it is pretty clear they are comparing to N5 family not N7. Density wise intel 4 trades blows with N5 family so clearly they must be comparing intel 3 to N3E family. For 18A they mentioned that it would beat the node they were comparing to market. I suppose that could theoretically be N3P, but that statement reads more like N2 to me.

Performance per watt at 1.2V is very different beast from PPW at Vmin. If we are talking about HPC only (which is what intel markets 18A non P as then I would assume PPW at high power is what they are talking about). IMO performance with no power constraints is a worthless metric. For CCG, sure it is important. But for HPC foundry or DCAI they want PPW not raw performance. If we want to talk about performance with unconstrained power intel 7 then I suppose you could say that it is the best node ever, and runs laps around N3. Of course no matter who you work for, you would rightfully laugh me out of the room if I said something so ignorant. For this reason I think it is important to delineate high vs low V PPW. Or maybe using the term power-performance to talk about low power PPW?

How so? Yield is yield, wafer cost is wafer cost. Yield can be improved to some asymptotic limit. Long term wafer cost post process ramp/depreciation is mostly determined by process flow decisions (i.e. you are stuck with it forever whereas yield is transient/evolving).

Interesting... prior recent projections I saw from you guys put 18A and N3 pretty close together (but maybe my brain is too heavily calibrated to the traditional 1.8-2X per node). As for N3-->N2 my assumption was that almost all of that 15% area improvement quoted is from the HD cell getting smaller than the N3E 2 fin device and all N2 devices being this way rather than what you have with N3 where only half of the devices are that 1 fin device. Put another way, on a theoretical basis (imperfect measurement, I know) the gap from 18A to N2 doesn't feel like it would be in "way ahead" territory. That is unless you mean by the standards of the difference is really big considering they are both 2"nm" class nodes and there is a big difference between them, rather than TSMC being 1.8-2X ahead. Although maybe this "way ahead" coming from a more nuanced definition of density in a more product like environment? If so I wonder if the high std cell utilization shown off by intel on intel 4+powervia will have real world density implications in excess of the theoretical improvement you see from reducing the number of M0 tracks? If things do pan out that way, then I have to assume that N2+BSPD can be an even bigger monster than I already think it could be.

Do your projections match up with their claim if we assume they are comparing 14A to N2+BSPD given that it feels like 2027 14A sounds to be slotting between N1.4 and that?

I have actual numbers for 18A pitches, I can't publish them but I can say that 18A high density cell transistors per mm2 are slightly higher than TSMC 5nm but lower than TSMC 3nm. To even catch up to TSMC 2nm, Intel 14A would need a big density jump and this is during a time when density jumps are getting harder.

 

[Scotten Jones]

They said they were comparing to the best node on the market at the time. Given ICL launched at EOY 2019 and TGL at EOY 2020, and they said intel 7 was far behind on density and performance it is pretty clear they are comparing to N5 family not N7. Density wise intel 4 trades blows with N5 family so clearly they must be comparing intel 3 to N3E family. For 18A they mentioned that it would beat the node they were comparing to market. I suppose that could theoretically be N3P, but that statement reads more like N2 to me.

Performance per watt at 1.2V is very different beast from PPW at Vmin. If we are talking about HPC only (which is what intel markets 18A non P as then I would assume PPW at high power is what they are talking about). IMO performance with no power constraints is a worthless metric. For CCG, sure it is important. But for HPC foundry or DCAI they want PPW not raw performance. If we want to talk about performance with unconstrained power intel 7 then I suppose you could say that it is the best node ever, and runs laps around N3. Of course no matter who you work for, you would rightfully laugh me out of the room if I said something so ignorant. For this reason I think it is important to delineate high vs low V PPW. Or maybe using the term power-performance to talk about low power PPW?

How so? Yield is yield, wafer cost is wafer cost. Yield can be improved to some asymptotic limit. Long term wafer cost post process ramp/depreciation is mostly determined by process flow decisions (i.e. you are stuck with it forever whereas yield is transient/evolving).

Interesting... prior recent projections I saw from you guys put 18A and N3 pretty close together (but maybe my brain is too heavily calibrated to the traditional 1.8-2X per node). As for N3-->N2 my assumption was that almost all of that 15% area improvement quoted is from the HD cell getting smaller than the N3E 2 fin device and all N2 devices being this way rather than what you have with N3 where only half of the devices are that 1 fin device. Put another way, on a theoretical basis (imperfect measurement, I know) the gap from 18A to N2 doesn't feel like it would be in "way ahead" territory. That is unless you mean by the standards of the difference is really big considering they are both 2"nm" class nodes and there is a big difference between them, rather than TSMC being 1.8-2X ahead. Although maybe this "way ahead" coming from a more nuanced definition of density in a more product like environment? If so I wonder if the high std cell utilization shown off by intel on intel 4+powervia will have real world density implications in excess of the theoretical improvement you see from reducing the number of M0 tracks? If things do pan out that way, then I have to assume that N2+BSPD can be an even bigger monster than I already think it could be.

Do your projections match up with their claim if we assume they are comparing 14A to N2+BSPD given that it feels like 2027 14A sounds to be slotting between N1.4 and that?

With respect to wafer cost the only yield that matters at all is line yield in the fab and everyone is in the high ninety percentiles. If you talk about die cost then die yield comes in and that is where Intel struggled at 14nm, and 10nm. Reportedly i4/i3 die yields are pretty good.

 

[Scotten Jones]

Here is Ian Cutress's take on it:

Intel Foundry: Realigning the Money

Full transition to Foundry revenues vs Product

morethanmoore.substack.com

Not 100% correct but very good for an outsider. I have been following Ian since he wrote at Anandtech. I see him at semiconductor events. He covers EDA now as well and was at the Synopsys User Group Meeting last month.

He said Intel has ~200k wpm starts, if that is correct their Fab utilization isn't good because they have a lot more capacity than that and they are adding more all the time.

 

[lefty]

18A high density cell transistors per mm2 are slightly higher than TSMC 5nm but lower than TSMC 3nm.

That's quite a bombshell, but it would explain a few things. It must have been a lot easier for Intel to get GAA and back side power to yield when the pitches are so relaxed. Also, if 18A is less than N3 then it must be only marginally more dense than Intel 4?

 

[MKWVentures]

When comparing wafer costs there are two components, one is process cost and the other is fab cost. Intel 10/7 processes are very expensive processes compared to TSMC 7nm even if run in the same fab. Intel fabs are generally in higher cost countries plus Intel has some Intel specific cost disadvantages. The net of this is Intel 10/7 cost is similar to TSMC selling price. The interesting thing is 18A as a process run in the same fabs as TSMC 2nm is actually a lower cost process, 18A is lower density and needs less EUV layers. Intel still has Fab cost issues but the cost to run 18A in Arizona Fab 52 versus TSMC 2nm in Fab 20-P1 is well below TSMC selling price. It is lower density but better raw performance so it depends on your needs.

Also, for the record all my wafer costs are calculated using the commercial models I sell that calibrate to published financials and inputs from a huge customer base. When I compare companies I always us the same depreciation rates to make it consistent.

We can talk about this but the challenge is that Intel just has Wafer cost. It includes everything. The issue for intel is typically the gap between your very accurate process model (It is unmatched) and what they actually do. Example: If Intel runs 10000 production wafers in a fab you think is capable of 20000 (for whatever reason.... uptime, engineering lots, tools not meeting spec, low demand, running expedites, whatever.... their cost skyrockets. I would be interested in what the models show for production wafers out per tool when comparing companies (I have a guess as to what it says).

We should wait to see what F52 actually does and what the wafer cost is when tools are installed and it is ramped. Some people may be surprised. With the new reporting method, it will be clear.... which is exactly what Pat wanted.

 

[MKWVentures]

He said Intel has ~200k wpm starts, if that is correct their Fab utilization isn't good because they have a lot more capacity than that and they are adding more all the time.

100% agree.

 

[VCT]

""Intel has outsourced about 30% of the total number of wafers to external contract manufacturers such as TSMC""

I can't see that in 2023 financial report of TSMC and also from Intel's current product line. Did he mean projects outsourced in 2023 and manufacture in 2024 and 2025.

 

[MKWVentures]

""Intel has outsourced about 30% of the total number of wafers to external contract manufacturers such as TSMC""

I can't see that in 2023 financial report of TSMC and also from Intel's current product line. Did he mean projects outsourced in 2023 and manufacture in 2024 and 2025.

30% of Intels wafers used are from TSMC in 2024. Meteor lake, Lunar lake, Arrow Lake, Panther lake 70% of the Silicon is TSMC with backup plans that can take that higher.

 

[Scotten Jones]

We can talk about this but the challenge is that Intel just has Wafer cost. It includes everything. The issue for intel is typically the gap between your very accurate process model (It is unmatched) and what they actually do. Example: If Intel runs 10000 production wafers in a fab you think is capable of 20000 (for whatever reason.... uptime, engineering lots, tools not meeting spec, low demand, running expedites, whatever.... their cost skyrockets. I would be interested in what the models show for production wafers out per tool when comparing companies (I have a guess as to what it says).

We should wait to see what F52 actually does and what the wafer cost is when tools are installed and it is ramped. Some people may be surprised. With the new reporting method, it will be clear.... which is exactly what Pat wanted.

What gap? I have done a ton of modeling of Intel over the years and confirmed/correlated results to published and private numbers. If a fab has a capacity of 100K wpm and is running 50K that is called utilization and it varies for all fabs, it is fully factored into my modeling. And while Intel utilization may be low right now, you would be shocked at what TSMC 5nm utilization ended last year at too.