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Intel 5N4Y info from SPIE AL 2024

H

hskuo

Well-known member
Here came more info about 5N4Y now, from intel Ann Kelleher in SPIE AL 2024.
1. intel 7 is in HVM
2. intel 4 is in HVM ramp
3. Intel 3 is manufacturing ready
4. intel 20A manufacturing ready in 2024
5. intel 18A Silicon goes into the fab in Q1 2024.
source: https://www.vibrantlightgallery.com/
1709448039948.png
 
Manufacturing ready in 2024 for 20A makes it sound like Arrow Lake won't be coming out this year. At least not with 20A.
 
HVM —> TSMC about 6 months before an iPhone first cycle say February the prior year.

HVM ramp —>. TSMC 9-12 months before an IPhone first cycle, my guess Sept - December the prior year

HVM ready —> 12-15 months before first iPhone ramp ~ January the prior year.

Do and RO performance to target are also very predictable, unless they have stooped to Samsung levels or this is a repeat of 10nm.

To think about it 4nm is the first real node since 10nm
 
Wasn't HA-EUV supposed to be a big part of angstrom level chips? Not to mention the contract Intel signed with TSMC to manufacture their 3nm CPUs. Intel keeps telling me 5N4Y is on-track, but I feel like we all envisioned something different when they announced it. Saying "Silicon goes into Fab Q1 2024" makes me think they are making product, not that they set a wafer inside the machine to start trying to calibrate the mirrors.
 
Sysreq said:
Wasn't HA-EUV supposed to be a big part of angstrom level chips? Not to mention the contract Intel signed with TSMC to manufacture their 3nm CPUs. Intel keeps telling me 5N4Y is on-track, but I feel like we all envisioned something different when they announced it. Saying "Silicon goes into Fab Q1 2024" makes me think they are making product, not that they set a wafer inside the machine to start trying to calibrate the mirrors.
Click to expand...
Yes - High NA EUV was originally going to be part of at least 18A, but they postponed that to 14A. 20A/18A will still be “Vanilla” EUV.
 
tooLongInEDA said:
What is "silicon goes into the fab" supposed to mean ? I'm more interested in when it comes out - preferably working.
Click to expand...
Usually A0 TI, after 3 months, PF skew corners and multiple baseline silicon finish characterization at SORT, Chip and system level probably between another couple dash stepping or in the case of one foundry many many all layer steppings. Comes down to how mature was the PDK, agressive timing and narrow window the platform has. No use ramping a low yielding like Samsung or Intel original 10nm.
 
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