Efficiency and sustainability are primary concerns for the production of devices that rely on semiconductors. As a result, research must be organized to find smarter approaches for material integration, device efficiency and long-term sustainability. During the Leti Devices Workshop, CEA-Leti experts will share their visions, innovations and achievements in the field of More than Moore …
The CHIPS Research and Development Office’s Chiplets Interfaces Technical Standards Workshop will be held as a hybrid in-person and virtual event from 8:30 a.m. to 5:30 p.m. Eastern Time December 12, 2023, and 8:30 am to 12:30 pm December 13, 2023. This event will bring together technical experts from industry, academia, standards setting organizations, and …
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About IWPSD 2023 The XXII International Workshop on the Physics of Semiconductor Devices (IWPSD 2023) is being jointly organized by the Indian Institute of Technology Madras in collaboration with Society for Semiconductor Devices and Semiconductor Society (India). This series of biennial workshops, started in 1981, provides a global forum for interaction between scientists and technologists …
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Technical standards for digital twin capabilities in the semiconductor and microelectronics industry will be the subject of a December workshop sponsored by the CHIPS Research and Development Office. The workshop will be a hybrid in-person and virtual event from 8:30 a.m. to 5:30 p.m. Eastern Time December 14, 2023, and 8:30 am to 12:30 pm …
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Description During the Photonics Workshop, CEA-Leti will unveil new breakthroughs in imaging and next generation displays. We will share and discuss the latest results in integrated photonics technology for communications, computing and sensing. This workshop offers you a unique opportunity to catch up on the latest cutting-edge research while networking with leading experts and industrial …
Day One - February 7 With the growing pervasiveness of artificial intelligence and machine learning (AI/ML), photonics is playing an increasingly important role in enabling AI transformation. We all know photonics is essential for communication, but how about computing? Can it help by not only moving data but also processing data? How? What are its advantages …
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Accellera at DVCon US 2024 Speaker: Richard Weber, Fellow, Director of Engineering, Arteris Anupam Bakshi, CEO, Agnisys Introduction: This tutorial explains basic usage of IP-XACT IEEE 1685-2022 for IP re-use and integration flows. Summary: This workshop explains the data model underlying the IP-XACT standard. This SoC data model unifies logical and physical connectivity as well as …
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Accellera at DVCon US 2024 Abstract: As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential risk mitigation strategies. We will then discuss …
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Accellera at DVCon US 2024 The implementation of Functional Safety standards such as ISO26262 poses challenges during the exchange and integration of functional safety data between different work products and activities, carried out by different teams and/or different layers of the supply chain. Automation with EDA tools is now common practice in this field, but …
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The Accellera UVM Working Group released the IEEE 1800.2-2020-2.0 reference library last year. Since that release, we have been working on a public Github repository to give users enhanced access to the latest bug fixes and to provide bug fix suggestions if they would like. Also, we have developed new, additive features to poll an …
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Accellera at DVCon US 2024 Authors: Jean-Philippe Martin, Intel Mike Borza, Synopsys Topic(s): Security Keywords: security, asset, accellera, sa-edi, IEEE P3164, threat modeling Abstract: This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation for Electronic Design Integration (SA-EDI) standard. This guidance is planned to be documented in the IEEE …
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Join the Cadence and AWS teams for a hands-on workshop and networking event to learn about the Cadence Cerebrus SaaS on AWS. All attendees will receive a giveaway and a chance to win raffle prizes. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization and has powered over 300 tapeouts. …
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