Date: Wednesday, June 7, 2023 Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models …
Continue reading "Webinar: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance"
Date: Wednesday, June 7, 2023 Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models …
Continue reading "CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance"
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the …
About DVCon China DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …
