A PI Engineer’s Guide to Up-Leveled Signoff Methodology

Online

August 26, 2021 Overview Power integrity (PI) engineers have been running Cadence®Sigrity™ tools to perform DC, AC, and power-ripple analysis for decades.  Sigrity X technology is recognized by the industry as simply the best to ensure that sufficient, efficient, and stable power is delivered to the components in your design.  Most Sigrity customers have in their tool chest a PI bundle …

IP Connectivity and Smart Assembly Methodology for SoCs

Online

Description Learn how to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise™. This includes automatic generation of components such as aggregators, bridges, channels, bus fabrics, muxes, etc. wherever needed. REGISTER HERE

DVCon: Sponsored Workshop: A Methodology for Power and Energy Efficient Systems Design

DoubleTree by Hilton Hotel San Jose 2050 Gateway Pl, San Jose, CA, United States

Power is everywhere. Traditionally, power used to be a concern with mobile and handheld devices due to battery life considerations. But now, power as a concern is prevalent in all verticals of the industry, for example, data centers consume huge amounts of power due to million of data transactions happening per second. Processors like CPUs …

SA-EDI Workshop: “A Practical Guide to SA-EDI Methodology”

DoubleTree by Hilton Hotel San Jose 2050 Gateway Pl, San Jose, CA, United States

Accellera at DVCon US 2024 Authors: Jean-Philippe Martin, Intel Mike Borza, Synopsys Topic(s): Security Keywords: security, asset, accellera, sa-edi, IEEE P3164, threat modeling Abstract: This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation for Electronic Design Integration (SA-EDI) standard.  This guidance is planned to be documented in the IEEE …

Webinar: Efficient Design Methodology for 112G Interface Compliance

Online

As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance, companies can take extra steps to …