DVCon: Sponsored Workshop: A Methodology for Power and Energy Efficient Systems Design
February 27 @ 1:30 PM - 3:30 PM
Power is everywhere. Traditionally, power used to be a concern with mobile and handheld devices due to battery life considerations. But now, power as a concern is prevalent in all verticals of the industry, for example, data centers consume huge amounts of power due to million of data transactions happening per second. Processors like CPUs and GPUs have always been power hungry but now with increased tiles and cores on these processors, the speeds are increasing manifolds which as result means significant rise in power dissipation. With 5G, edge computing and IoT, the devices are becoming compute intensive leading to more power consumption. And last but not the least, automotive. In cars, there is now a lot more electronics than it used to be, consuming a lot of power and generating a lot of heat.
In this workshop, I will be demonstrating why early RTL power and energy estimations are key metrics and how the two metrics have taken a center stage lately in performance-sensitive system design considerations. I will be talking about the RTL Power Analysis as a solution and the challenges associated with it. Also, I would be proposing a regression-ready, error-correcting and fully seamless methodology for an early Power closure at RTL level. I will discuss the key aspects of this methodology like With ever-increasing chip design complexity, including chips for domain-specific applications, the role of on-chip and off-chip protocols.
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