flows

Date: Tuesday, June 14, 2022 Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally lead …

Continue reading "Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows"

Date: Thursday, June 16, 2022 Time: 11:00am - 12:00pm (PDT) Overview System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, …

Continue reading "Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows"