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CadenceTECHTALK: Taming the Challenges of Advanced Node Digital Designs

Online

Taming the Challenges of Advanced Node Digital Designs November 10, 2021 Overview Although new challenges arise with each node, the move from bulk technologies to advanced node technologies marks a distinctive shift in complexity. Some of the important factors to consider are new devices, challenging and competing design rules, double patterning, managing of the layout …

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CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis

Online

Date: Tuesday, September 20, 2022 Time: 10:00 - 11:00 (CEST) Electromigration (EM) impacts design reliability, causing failures over time. That is why it’s important to analyze both the power mesh and signal wires to check that the average, rms, or peak currents will not lead to a permanent failure. Learn how the Cadence Voltus IC Power …

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Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

Online

Synopsys Webinar | Tuesday, September 20, 2022 | 10 a.m. Pacific Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are of little value if they cannot …

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Webinar: Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

Online

Summary The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static design verification is an essential part of a robust verification process that includes advanced linting and Clock Domain Crossing (CDC) analysis. In this webinar, we …

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LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 3: Advanced Testbench for a Complex DUT (US)

Online

Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more …

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