Wednesday, April 5, 2023 | 10:00 - 11:00 a.m. Pacific Over the last few decades System on Chip (SoC) design size has dramatically increased, and more complexity has been introduced …
Continue reading "Webinar: Shorten Your CDC Debug Cycle by 10X with ML-based RCA"
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in …
Continue reading "Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers"
*Please use your work email so we know who the audience is* Various IP blocks within an SoC are often required to work in different clock domains in order to …
Accellera at DVCon US 2024 Abstract: As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers …
Continue reading "CDC Workshop: “Hierarchical CDC and RDC Closure with Standard Abstract Models”"
